AD9806KST Analog Devices Inc, AD9806KST Datasheet - Page 4

• Manufacturer Part Number: AD9806KST
• Description: IC CCD SIGNAL PROC 10BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9806KST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9806–SPECIFICATIONS
AUX-MODE SPECIFICATIONS
Parameter
POWER CONSUMPTION
MAXIMUM CLOCK RATE
PGA (Gain Selected through Serial Interface F-Reg)
ACTIVE CLAMP
TIMING SPECIFICATIONS
NOTES
1
Specifications subject to change without notice.
AUXMID-MODE SPECIFICATIONS
Parameter
POWER CONSUMPTION
MAXIMUM CLOCK RATE
PGA (Gain Selected through Serial Interface F-Reg)
MIDSCALE OFFSET LEVEL (AT MAX PGA GAIN)
TIMING SPECIFICATIONS
NOTES
1
Specifications subject to change without notice.
20 pF loading; timing shown in Figure 2.
20 pF loading; timing shown in Figure 2.
Normal (D-Reg 00)
High-Speed (D-Reg 01)
Normal (D-Reg 00)
High-Speed (D-Reg 01)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Range
Clamp Level (Selected through Serial Interface E-Reg)
Pipeline Delay
Internal Clock Delay (t
Output Delay (t
Output Hold Time (t
Max Input Range
Max Output Range
Gain Control Resolution
Gain Range (See Figure 5b for Gain Curve)
Pipeline Delay
Internal Clock Delay (t
Output Delay (t
Output Hold Time (t
Min Gain (Code 128)
Max Gain (Code 255)
CLP0 (E-Reg 00)
CLP1 (E-Reg 01)
CLP2 (E-Reg 10)
CLP3 (E-Reg 11)
Min Gain (Code 512)
Max Gain (Code 1023)
OD
OD
)
)
HOLD
HOLD
ID
ID
)
)
)
)
1
1
(T
MIN
to T
(T
MIN
MAX
to T
, AVDD = DVDD = 3.0 V, f
MAX
, AVDD = DVDD = 3.0 V, f
Min
18
28.6
700
1000
7
Min
18
700
1000
462
7
ADCCLK
= 18 MHz, unless otherwise noted.)
ADCCLK
Typ
50
95
7
–2
15
32
48
64
16
9
14.5
Typ
50
9
–4
14
512
9
14.5
= 18 MHz, unless otherwise noted.)
Max
16
Max
562
16
Unit
mW
mW
MHz
MHz
mV p-p
mV p-p
Bits
dB
dB
LSB
LSB
LSB
LSB
Cycles
ns
ns
Unit
mW
MHz
mV p-p
mV p-p
Bits
dB
dB
LSB
Cycles
ns
ns