PCA9698DGG,512 NXP Semiconductors, PCA9698DGG,512 Datasheet - Page 27

• Manufacturer Part Number: PCA9698DGG,512
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9698DGG,512

• Package / Case: 56-TSSOP
• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9698
• Number Of Lines (input / Output): 40.0 / 40.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I2C Bus
• Maximum Clock Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 40.0
• Number Of Output Lines: 40.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6281 - DAUGHTER CARD PCA9698 FOR OM6275
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3241-5; 935278614512; PCA9698DGG

NXP Semiconductors
PCA9698
Product data sheet
Fig 16. Write to a specific output port
Fig 17. Write to the I/O Configuration, Polarity Inversion, or Mask interrupt registers (5 banks)
OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs.
OCH = 0. When OCH = 1, the change in the port happens at the acknowledge phase.
Two, three, or four adjacent banks can be programmed by using the Auto-Increment feature (AI = 1) and change at the
corresponding output port becomes effective at the STOP command when OCH = 0, or at each acknowledge when OCH = 1.
The programing becomes effective at the Acknowledge.
Less than 5 bytes can be programmed by using the same scheme. ‘D5 D4 D3 D2 D1 D0’ refers to the first register to be
programmed.
If more than 5 bytes are written, previous data are overwritten (the sixth configuration register will roll over to the first addressed
configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion register, the sixth
Mask interrupt register will roll over to the first addressed Mask interrupt register.
SDA
write to port
data out from port
SDA
S A6 A5 A4 A3 A2 A1 A0 0 A
START condition
S A6 A5 A4 A3 A2 A1 A0 0 A
START condition
slave address
slave address
acknowledge
from slave
R/W
R/W
All information provided in this document is subject to legal disclaimers.
acknowledge
from slave
AI 0
AI = 1
1
0 D5 D4 D3 D2 D1 D0
40-bit Fm+ I
Rev. 3 — 3 August 2010
command register
0
0
DATA BANK 2 A
1 D2 D1 D0
acknowledge
from slave
2
01 0000 for Polarity Inversion register programming bank 0
01 1000 for Configuration register programming bank 0
10 0000 for Mask interrupt register programming bank 0
C-bus advanced I/O port with RESET, OE and INT
A
A
acknowledge
from slave
acknowledge
from slave
DATA BANK 0 A
DATA BANK 3 A
determined by
DATA BANK X
D2, D1, D0
bank X
condition
acknowledge
from slave
acknowledge
from slave
STOP
DATA BANK 1
DATA BANK 4
A
acknowledge
from slave
P
t
v(Q)
condition
STOP
A
A
acknowledge
from slave
acknowledge
from slave
data X valid
002aab946
PCA9698
P
002aab945
© NXP B.V. 2010. All rights reserved.
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