PCA9698DGG,512 NXP Semiconductors, PCA9698DGG,512 Datasheet - Page 11

• Manufacturer Part Number: PCA9698DGG,512
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9698DGG,512

• Package / Case: 56-TSSOP
• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9698
• Number Of Lines (input / Output): 40.0 / 40.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I2C Bus
• Maximum Clock Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 40.0
• Number Of Output Lines: 40.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6281 - DAUGHTER CARD PCA9698 FOR OM6275
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3241-5; 935278614512; PCA9698DGG

NXP Semiconductors
Table 4.
Legend: * default value ‘X’ determined by the externally applied logic level.
Table 5.
Legend: * default value.
PCA9698
Product data sheet
Address
00h
01h
02h
03h
04h
Address
08h
09h
0Ah
0Bh
0Ch
IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Register
IP0
IP1
IP2
IP3
IP4
Register
OP0
OP1
OP2
OP3
OP4
7.4.1 IP0 to IP4 - Input Port registers
7.4.2 OP0 to OP4 - Output Port registers
These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to
these registers have no effect.
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of
the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0.
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
All information provided in this document is subject to legal disclaimers.
Symbol
I0[7:0]
I1[7:0]
I2[7:0]
I3[7:0]
I4[7:0]
Symbol
O0[7:0]
O1[7:0]
O2[7:0]
O3[7:0]
O4[7:0]
40-bit Fm+ I
Rev. 3 — 3 August 2010
Access
R
R
R
R
R
Access
R/W
R/W
R/W
R/W
R/W
2
C-bus advanced I/O port with RESET, OE and INT
0000 0000*
0000 0000*
0000 0000*
0000 0000*
0000 0000*
Value
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
Value
Input Port register bank 0
Input Port register bank 1
Input Port register bank 2
Input Port register bank 3
Input Port register bank 4
Description
Description
Output Port register bank 0
Output Port register bank 1
Output Port register bank 2
Output Port register bank 3
Output Port register bank 4
PCA9698
© NXP B.V. 2010. All rights reserved.
11 of 48