ADV7321KSTZ Analog Devices Inc, ADV7321KSTZ Datasheet - Page 42

• Manufacturer Part Number: ADV7321KSTZ
• Description: IC VID ENC 6-12BIT DAC'S 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7321KSTZ

• Applications: EVD, DVD, SD/PS/HDTV
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 2.375V To 2.625V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7320/ADV7321
HD ASYNC TIMING MODE
[Subaddress 0x10, Bits 3 and 2]
For any input data that does not conform to the standards
selectable in input mode (Subaddress 0x10) asynchronous
timing mode can be used to interface to the ADV7320/ADV7321.
Timing control signals for HSYNC , VSYNC , and BLANK must
be programmed by the user. Macrovision and programmable
oversampling rates are not available in async timing mode.
Table 26. Async Timing Mode Truth Table
P_HSYNC
1 → 0
0
0 → 1
1
1
1
When async timing mode is enabled, P_BLANK , Pin 25, becomes an active high input. P_BLANK is set to active low at Address 0x10, Bit 6.
SET ADDRESS 0x14,
SET ADDRESS 0x14
ANALOG OUTPUT
P_VSYNC
0
0 → 1
0 or 1
0 or 1
0 or 1
P_HSYNC
P_BLANK
P_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
BIT 3 = 1
BIT 3 = 1
CLK
CLK
P_BLANK
0 or 1
0 or 1
0
0 → 1
1 → 0
Figure 58. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
81
Figure 59. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
1
a
a
HORIZONTAL SYNC
Reference
50% point of falling edge of trilevel horizontal sync signal
25% point of rising edge of trilevel horizontal sync signal
50% point of falling edge of trilevel horizontal sync signal
50% start of active video
50% end of active video
66
HORIZONTAL SYNC
b
b
66
c
c
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243
In async mode, the PLL must be turned off [Subaddress 0x00,
Bit 1 = 1]. Register 0x10 should be programmed to 0x01.
Figure 58 and Figure 59 show examples of how to program the
ADV7320/ADV7321 to accept a high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R
BT.1358.
Follow the specifications in Table 26 when programming the
control signals in async timing mode. For standards that do not
require a trisync level, P_BLANK must be tied low at all times.
d
d
ACTIVE VIDEO
1920
ACTIVE VIDEO
Reference in Figure 58 and Figure 59
a
b
c
d
e
e
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
e
0
1