ADV7321KSTZ Analog Devices Inc, ADV7321KSTZ Datasheet - Page 28

• Manufacturer Part Number: ADV7321KSTZ
• Description: IC VID ENC 6-12BIT DAC'S 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7321KSTZ

• Applications: EVD, DVD, SD/PS/HDTV
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 2.375V To 2.625V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7320/ADV7321
Table 10. Register 0x12
SR7–
SR0
0x12
Table 11. Registers 0x13 to 0x14
SR7–
SR0
0x13
0x14
1
2
Used in conjunction with HD_SYNC in Register 0x02, Bit 7, set to 1.
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Register
HD Mode
Register 4
HD Mode
Register 5
Register
HD Mode
Register 3
Bit Description
HD Cr/Cb Sequence
Reserved
HD Input Format
Sinc Filter on DAC D, E, F
Reserved
HD Chroma SSAF
HD Chroma Input
HD Double Buffering
HD Timing Reset
HD Hsync Generation
HD Vsync Generation
HD Blank Polarity
HD Macrovision for
525p and 625p
Reserved
HD VSYNC /Field Input
Horizontal/Vertical
Counters
Bit Description
HD Y Delay with
Respect to Falling
Edge of HSYNC
HD Color Delay with
Respect to Falling
Edge of HSYNC
HD CGMS
HD CGMS CRC
2
1
1
0
1
0
1
Bit 7
0
1
Bit 7
Bit 6
0
1
0
1
Bit 6
0
1
Bit 5
0
1
0
Bit 5
0
0
0
0
1
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Bit 4
0
0
1
Bit 4
0
0
1
1
0
Bit 3
0
1
0
1
Bit 3
0
1
0
1
0
Bit 2
0
1
0
1
Bit 2
0
0
0
1
0
Bit 1
0
0
1
Bit 1
0
0
1
1
0
Bit 0
1
0
x
Bit 0
0
1
0
1
0
Register Setting
Cb after falling edge of HSYNC .
Cr after falling edge of HSYNC .
0 must be written to this bit.
8-bit input.
10-bit input.
Disabled.
Enabled.
0 must be written to this bit.
Disabled.
Enabled.
4:4:4
4:2:2
Disabled.
Enabled.
A low-high-low transition resets
the internal HD timing counters.
Refer to the HSYNC / VSYNC
Output Control section.
BLANK active high.
BLANK active low.
Macrovision disabled.
Macrovision enabled.
0 must be written to these bits.
0 = field input.
1 = VSYNC input.
Update field/line counter.
Field/line counter free running.
Register Setting
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
4 clock cycles
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
4 clock cycles
Disabled
Enabled
Disabled
Enabled
Reset
Values
0x00
Reset
Values
0x4C
0x00