BU1425AKV Rohm Semiconductor, BU1425AKV Datasheet

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... Multimedia ICs NTSC / PAL digital RGB encoder BU1425AK / BU1425AKV The BU1425AK / BU1425AKV are ICs which convert digital RGB / YUV input to composite (NTSC / PAL / PAL60), luminance (Y), and chrominance (C) signals, and outputs the results. • Applications Video interfaces for VIDEO-CDs and CD-G decoders • ...

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... LATCH RGB YUV VCLK RSTB 2 RGB 24BITS Y-LEVEL ADJ UV FILTER CHROMA GEN VIDEO TIMING CONTROL SUB CARRIER BURST GENERATOR MODE CONTROL FIELD / FLAME CONTROL BU1425AK / BU1425AKV DAC Y-FILTER MIX SIG V and sync Y burst C C-FILTER SYNC BLANK BURST VOUT YOUT COUT PIXCLK ...

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... BU1425AK / BU1425AKV Function SLABEB SELECT MASTER / SLAVE ADDH + 0.5 / – 0.5LINE at NON-INTER VREF-C DAC BIAS CGND CHROMA OUTPUT GROUND COUT CHROMA OUTPUT VGND Composite Output Ground VOUT COMPOSITE OUTPUT AV Analog Ground (DAC VREF) SS P-V POWER (DAC REFERENCE RESISTOR AV ANALOG (VREF YGND ...

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... LSB — 25.14 — — 7.24 — – 10 0.0 10.0 — 25.14 — — 7.24 — – 10 0.0 10.0 — — 1.0 BU1425AK / BU1425AKV Unit Unit 5.0V, GND = AV = VGND = CGND = YGND Unit Conditions mA 27MHz color bar mA 27MHz color bar PD mode ...

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... BD4 17 BD5 18 BD6 19 BD7 20 GND 21 NTB 22 IM0 23 IM1 24 BU1425AK / AKV TEST1 25 TEST2 26 VSY 27 HSY 28 PIXCLK INT 32 Fig.1 BU1425AK / BU1425AKV GOSD 64 7 RD7 63 6 RD6 RD5 60 4 RD4 59 3 RD3 58 ROSD 57 2 RD2 56 1 RD1 55 0 RD0 54 CLKSW 53 RSTB 52 VCLK 51 PAL GOB ...

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... BD4 17 BD5 18 BD6 19 BD7 20 GND 21 NTB 22 IM0 23 IM1 24 BU1425AK / AKV TEST1 25 TEST2 26 VSY 27 HSY 28 PIXCLK INT 32 0.01 F Fig.2 BU1425AK / BU1425AKV GOSD 64 7 RD7 63 6 RD6 RD5 60 4 RD4 59 3 RD3 58 ROSD 57 2 RD2 56 1 RD1 55 0 RD0 54 CLKSW 53 RSTB 52 YCLK 51 PAL GOB ...

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... IM1 16 CDGSWB I 22 NTB I BU1425AK / BU1425AKV Equivalent circuit G data input pin for 24-bit RGB input Y data input pin for 16-bit YUV input B data input pin for 24-bit RGB input U, V data input pins for 16-bit YUV input R data input pin for 24-bit RGB input OSD data input pin when using the OSD function ...

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... ADDH I 35 VREF COUT O 8 BU1425AK / BU1425AKV Equivalent circuit This is the horizontal synchronization signal pin. Negative polarity Hsync signals are input (when SLABEB = LOW) or output (when SLABEB = HIGH) here. This is also used as the synchronization signal for fixing the PIXCLK output phase. ...

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... I 52 RSTB I YFILON1B 49 I YFILON2B BU1425AK / BU1425AKV Equivalent circuit Composite output pin Luminance output pin for the S pin The output amplitude (output current for 1 LSB) of the DAC is specified using an external resistor, and this pin controls the value of the current flow- ing per bit. ...

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... YGND BU1425AK / BU1425AKV Equivalent circuit Switches between the PAL and PAL60 modes. This is effective only when the NTB pin is HIGH. (PAL mode only) This switches between dividing the VCLK input in half and using internal clock (when LOW), and using internal clock without dividing it in half (when HIGH) ...

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... Output Mode and Power Consumption VOUT pin YOUT pin Composite signal Luminance signal Composite signal No output (0V) BU1425AK / BU1425AKV output can P-P to the VOUT pin as an terminus) is connected, the output is voltage output at a white 100% P-P COUT pin Power consumption (typ.) Chrominance signal 0 ...

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... HIGH, the number of lines in one field is set to the number of interlace output lines plus 0.5 lines. Scan Mode Non-interlace Non-interlace Interlace Input format R (8 bits bits bits) 16-bit YUV ( — ROSD, GOSD, BOSD expanded to RGB input BU1425AK / BU1425AKV TV mode CD-G NTSC NTSC CD-G PAL60 PAL60 CD-G PAL PAL No ...

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... HSY is output at the timing shown in Fig. 3. With the BU1425AK, data (RD, GD, BD, etc.) is read at the ris- ing edge of the internal clock (BCLK), so data should be input to the BU1425AK / AKV as shown in Fig. 3. Fig. 3 Illustration of clock timing (CLKSW is LOW) BU1425AK / BU1425AKV BIT3 BIT2 BIT1 BIT0 ...

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... LOW). When using the non-interlace mode, operation is normally carried out under odd field condi- tions (the falling edges of Hsy and Vsy are simultane- ous). BU1425AK / BU1425AKV CD-G Mode NTSC PAL / PAL60 28.636MHz 28 ...

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... Fig.6 chart2 (BCLK = 13.5MHz) 180 135 – 45 – 90 – 135 – 180 10000 20000 BU1425AK / BU1425AKV chart1 chart2 chart3 180 135 – 45 – 90 – 135 – 180 1000 10000 20000 FREQUENCY (kHz) Gain-Phase Graphic ...

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... DAC output when the color bars from the various pins are reproduced. BLACK LEVEL 16 BLACK LEVEL = PEDESTAL LEVEL SYNC TIP LEVEL Fig. 8 YOUT output COLOR BURST Fig. 9 COUT output BLACK LEVEL = PEDESTAL LEVEL SYNC TIP LEVEL Fig. 10 VOUT output BU1425AK / BU1425AKV WHITE YELLOW CYAN GREEN MAGEN RED BLUE BLACK ...

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... NTSC / PAL mode switching pin I PAL / PAL60 mode switching pin I Interlace / Non-interlace mode switching pin I Master / Slave mode switching pin I Pin which adds 1 line in non-interlace mode divider output for internal clock (OSD clock) BU1425AK / BU1425AKV YOUT COUT 000 — — 033 — 038 — 100 ...

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... RSTB pin (pin 52). Table 11 Parameter Data setup time 1 18 data is read and discharged at the rising edge of the internal clock. The illustration below shows the input con- ditions in the various modes. Fig.11 Symbol Min. Typ. Tds1 10 — BU1425AK / BU1425AKV Tds1 Max. — ...

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... Data setup time 2 3. Slave mode, 1 clock mode Encoder slave (pin Internal clock = input clock (pin VCLK (pin53) Internal clock (BCLK) Input data Input data (HSY, VSY) Fig.12 Symbol Min. Typ. Tds2 10 — Tsh1 Tsd1 Fig.13 BU1425AK / BU1425AKV Tds2 Max. — Tds3S Tds3H 19 ...

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... Sync signal hold time 2 Sync signal setup time 2 20 Symbol Min. Typ. Tds3S 5 — Tds3H 8 — Tsd1 5 — Tsh1 8 — Tsh2 Tsd2 Fig.14 Symbol Min. Typ. Tds4 10 — Tsh2 10 — Tsd2 10 — BU1425AK / BU1425AKV Max. — — — — Tds4 Max. — — — ...

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... HSY, as shown in Fig.15. (In the Encoder Master mode, phase correction is implemented using the HSY output of the BU1425AK itself.) The OSD function is effective only during the time that video output is enabled. (See the TV signal timing diagram on page 27.) VIDEO-DATA Fig. 15 Clock timing with the OSD function BU1425AK / BU1425AKV BLACK YELLOW VIDEO-DATA 21 ...

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... Tvdf PIXCLK (OUT) Tpdr Table 15 Parameter HSY output delay VSY output delay PIXCLK output delay 22 Thdr Fig. 16 Output timing with a doubled clock Symbol Min. Typ. Thdr Thdf — 14 Tvdr Tvdf — 14 Tpdr Tpdf — 14 BU1425AK / BU1425AKV Tvdr Max. — — — ...

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... PIXCLK (OUT) Tpdr Table 16 Parameter HSY output delay VSY output delay PIXCLK output delay Thdr Fig. 17 Output timing with a clock at the regular frequency Symbol Min. Typ. Thdr Thdf — 10 Tvdr Tvdf — 10 Tpdr Tpdf — 10 BU1425AK / BU1425AKV Tvdr Max. — — — 23 ...

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... Odd input conditions are indicated below. Timing that does not match these conditions is recog- nized as an even field. Tvl Thvdiff Fig. 18 Odd recognition conditions Unit Min. Typ. BCLK 128 — HSY falling edge HSY Rising edge BCLK — – 1clk BU1425AK / BU1425AKV Max. — – 2clk ...

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... VSYNC is input in even fields. Expanded view Fhsync The middle of HSY Fhsync Thvdiff Fig. 19 Even conditions Unit Min. Typ. BCLK 128 — The middle of HYS BCLK — – 128clk BU1425AK / BU1425AKV Tvl Max. — HSY Falling edge – 128clk 25 ...

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... Td5 26 Td5 Fig signal timing diagram NTSC Unit V-CD CD-G BCLK 64 67 BCLK 71 76 BCLK 106 112 BCLK 128 135 BCLK 858 910 BU1425AK / BU1425AKV BURST BURST PAL PAL60 V-CD CDG1 V-CD CDG1 106 112 106 142 149 128 864 908 ...

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... Multimedia ICs Frame timing in Video-CD mode (NTSC / PAL60: Interlace) BU1425AK / BU1425AKV Fig ...

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... Multimedia ICs Frame timing in Video-CD mode (PAL: Interlace) 28 BU1425AK / BU1425AKV Fig.22 ...

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... Multimedia ICs Frame timing in CD-G mode (NTSC / PAL60: Non-interlace) BU1425AK / BU1425AKV Fig.23 29 ...

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... Multimedia ICs Frame timing in CD-G mode (PAL: Non-interlace) 30 BU1425AK / BU1425AKV Fig.24 ...

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... At that time, the timing of U and V can be reversed when data is input, using the state of the Test2 pin. The input conditions for this mode are shown below Fig. 25 YUV input timing when TEST[ Fig. 26 YUV input timing when TEST[ BU1425AK / BU1425AKV is obtained. P ...

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... In a doubled clock mode, the timing of U and shown in Fig. 7- regular clock mode, the timing of U and shown in Fig. 7- doubled clock mode, the timing of U and shown in Fig. 7- regular clock mode, the timing of U and shown in Fig. 7-2. BU1425AKV 0.15 0.1 0.15 BU1425AK / BU1425AKV 12.0 0.3 10.0 0 ...

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Appendix No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product ...