ADV7189BKSTZ Analog Devices Inc, ADV7189BKSTZ Datasheet - Page 12

• Manufacturer Part Number: ADV7189BKSTZ
• Description: IC DECODER VIDEO W/ADC 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7189BKSTZ

• Applications: Set-Top Boxes, Video Players, Recorders
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 12bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• Power Dissipation Pd: 450mW
• No. Of Input Channels: 12
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7189B
Table 7. Pin Function Descriptions
Pin No.
3, 9, 14, 31, 71
39, 40, 47, 53,
56
4, 15
10, 30, 72
50
38
42, 44, 46, 58,
60, 62, 41, 43,
45, 57, 59, 61
11
13, 16, 25, 63,
65, 69, 70, 77,
78
35 to32, 24 to
17, 8 to 5,
76 to 73
2
1
80
67
68
66
64
27
26
29
28
36
79
37
12
51
52
48, 49
54, 55
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
AIN1toAIN12
INTRQ
NC
P0–P19
HS
VS
FIELD
SDA
SCLK
ALSB
RESET
LLC1
LLC2
XTAL
XTAL1
PWRDN
OE
ELPF
SFL
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
Type
G
G
P
P
P
P
I
O
O
O
O
O
I/O
I
I
I
O
O
I
O
I
I
I
O
O
O
I
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in
No Connect Pins.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
I
I
This pin selects the I
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7189B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7189B. Nominally 27 MHz,
but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7189B.
Nominally 13.5 MHz, but varies up or down according to video line length.
This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7189B. In crystal mode, the crystal
must be a fundamental crystal.
A logic low on this pin places the ADV7189B in a power-down mode. Refer to Power
Management Register in the
modes for the ADV7189B.
When set to a logic low, OE enables the pixel output bus, P19 toP0 of the ADV7189B. A logic
high on the OE pin places Pins P19 to P0, HS, VS, SFL into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
F igure 46.
1 3 4 H
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video
encoder.
Internal Voltage Reference Output. Refer to
this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to
ADC’s Capacitor Network. Refer to
2
2
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input (Max Clock Rate of 400 kHz).
Rev. B | Page 12 of 104
2
C address for the ADV7189B. ALSB set to a Logic 0 sets the address for a
I 2C Register Maps section for more options on power-down
1 3 3 H
F igure 46 for a recommended capacitor network for this pin.
1 3 7 H
F igure 46 for a recommended capacitor network for this pin.
1 3 8 H
T able 86.
1 3 2 H
F igure 46 for a recommended capacitor network for
1 3 5 H
F igure 46 for a
1 3 6 H