ADV7180BSTZ Analog Devices Inc, ADV7180BSTZ Datasheet - Page 100

• Manufacturer Part Number: ADV7180BSTZ
• Description: IC VIDEO DECODER SDTV 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180BSTZ

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Resolution (bits): 10bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 57.27MSPS
• Power Dissipation Pd: 15µW
• No. Of Input Channels: 6
• Supply Voltage Range: 1.71V To 1.89V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7180
Address Register
0x4A
0x4B
0x4C
0x4E
Interrupt Status 3
(read only)
Interrupt Clear 3
(write only)
Interrupt Mask 3
(read/write)
Interrupt Status 4 (read only)
User Sub Map
Bit Description
SD_OP_CHNG_Q; SD 60 Hz/50 Hz
frame rate at output
SD_V_LOCK_CHNG_Q
SD_H_LOCK_CHNG_Q
SD_AD_CHNG_Q; SD autodetect
changed
SCM_LOCK_CHNG_Q; SECAM lock
PAL_SW_LK_CHNG_Q
Reserved
SD_OP_CHNG_CLR
SD_V_LOCK_CHNG_CLR
SD_H_LOCK_CHNG_CLR
SD_AD_CHNG_CLR
SCM_LOCK_CHNG_CLR
PAL_SW_LK_CHNG_CLR
Reserved
SD_OP_CHNG_MSK
SD_V_LOCK_CHNG_MSK
SD_H_LOCK_CHNG_MSK
SD_AD_CHNG_MSK
SCM_LOCK_CHNG_MSK
PAL_SW_LK_CHNG_MSK
Reserved
VDP_CCAPD_Q
Reserved
VDP_CGMS_WSS_CHNGD_Q; see
0x9C Bit 4 of user sub map to determine
whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
Reserved
VDP_GS_VPS_PDC_UTC_CHNG_Q;
see 0x9C Bit 5 of User Sub Map to deter-
mine whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
Reserved
VDP_VITC_Q
Reserved
Rev. F | Page 100 of 116
7 6 5 4 3 2 1 0
x x
x x
x x
x
Bit
0
1
(Shading Indicates
Default State)
0
1
0
1
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
0
1
0
1
0
1
0
1
Comments
No change in SD signal standard
detected at the output
No change in SD
Not used
Masks SD_OP_CHNG_Q bit
Masks SD_H_LOCK_CHNG_Q bit
Not used
Closed captioning not detected
VITC data is not available in the VDP
A change in SD signal standard is
detected at the output
SD
No change in
SD
No change in AD_RESULT[2:0] bits in
Status 1 register
AD_RESULT[2:0] bits in Status 1 register
have changed
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging burst
lock status
PAL swinging burst lock status has
changed
Not used
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
Clears SD_AD_CHNG_Q bit
Do not clear
Clears SCM_LOCK_CHNG_Q bit
Do not clear
Clears PAL_SW_LK_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q bit
Closed captioning detected
CGMS/WSS data is not changed/
not available
CGMS/WSS data is changed/available
Gemstar/PDC/VPS/UTC data is not
changed/not available
Gemstar/PDC/VPS/UTC data is
changed/available
VITC data is available in the VDP
VSYNC
HSYNC
lock status has changed
lock status has changed
HSYNC
VSYNC
lock status
lock status
Notes
These bits can be cleared
and masked by
Register 0x4B and
Register 0x4C, respectively
These bits can be cleared
and masked by Register
0x4F and Register 0x50,
respectively; note that an
interrupt in Register 0x4E
for the CCAP, Gemstar,
CGMS, WSS, VPS, PDC,
UTC, and VITC data uses
the VDP data slicer