ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 106

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
7.3.4 Interrupt Management
The interrupts of the Extended Function Timer are
mapped on the eight external interrupt channels of
the microcontroller (refer to the “Interrupts” chap-
ter).
Depending on device specification, one of the fol-
lowing configurations can occur:
– The three interrupt sources are mapped on three
– The three interrupt sources are mapped on the
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
– A pending bit in the EIPR register (R243 -
– A mask bit in the EIMR register (R244 - Page 0)
Program the interrupt priority level using the
EIPLR register (R245 - Page 0). For a description
of these registers refer to the “Interrupts” and
“DMA” chapters.
Use of three interrupt channels
To use the interrupt features, for each interrupt
channel used, perform the following sequence:
– Set the priority level of the interrupt channel(s)
– Select the interrupt trigger edge(s) as rising edge
– Set the OCIS and/or ICIS and/or TOIS bit(s) of
– Set the OCIE and/or ICIE and/or TOIE bit(s) of
– In the EIPR register, reset the pending bit(s) of
– Set the mask bit(s) of the interrupt channel(s)
106/179
different interrupt channels (to use this feature,
the EFTIS bit must be reset)
same interrupt channel (to use this feature, the
EFTIS bit must be set)
Page 0)
Page 0)
used for the Extended Function Timer (EIPRL
register)
(set the corresponding bit(s) in the EITR register)
the CR3 register to select the peripheral interrupt
source(s)
the CR1 register to enable the peripheral to per-
form interrupt requests on the desiderate events
the interrupt channels used by the peripheral in-
terrupts to avoid any spurious interrupt requests
being performed when the mask bit(s) is/are set
used to enable the MCU to acknowledge the in-
terrupt requests of the peripheral.
9
Use of one external interrupt channel for all the
interrupts
To use the interrupt features, perform the following
sequence:
– Set the priority level of the interrupt channel used
– Select the interrupt trigger edge as rising edge
– Set the EFTIS bit of the CR3 register to select
– Set the OCIE and/or ICIE and/or TOIE bit(s) of
– In the EIPR register, reset the pending bit of the
– Set the mask bits of the interrupt channels used
Caution: Care should be taken when using only
one of the input capture pins, as both capture in-
terrupts are enabled by the ICIE bit in the CR1 reg-
ister. If only ICAP1 is used (for example), an inter-
rupt can still be generated by the ICAP2 pin when
this pin toggles, even if it is configured as a stand-
ard output. If this case, the interrupt capture status
bits in the SR register should handled in polling
mode.
Caution:
1. It is mandatory to clear all EFT interrupt flags
2. Since a loop statement is needed inside the IT
(EIPRL register)
(set the corresponding bit in the EITR register)
the peripheral interrupt sources
the CR1 register to enable the peripheral to per-
form interrupt requests on the wanted events
interrupt channel used by the peripheral inter-
rupts to avoid any spurious interrupt requests be-
ing performed when the mask bits is set
to enable the MCU to acknowledge the interrupt
requests of the peripheral.
simultaneously at least once before exiting an
EFT timer interrupt routine (the SR register
must = 00h at some point during the interrupt
routine), otherwise no interrupts can be issued
on that channel anymore.
Refer to the following assembly code for an
interrupt sequence example.
routine, the user must avoid situations where
an interrupt event period is narrower than the
duration of the interrupt treatment. Otherwise
nested interrupt mode must be used to serve
higher priority requests.