ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 100

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
7.3.3.3 Input Capture
In this section, the index, i , may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAP i pin (see figure 5).
IC i Rregister is a read-only register.
The active transition is software programmable
through the IEDG i bit of the Control Register (CR i ).
Timing resolution is one count of the free running
counter: (
Procedure
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0] (see
– Select the edge of the active transition on the
And select the following in the CR1 register:
100/179
Clock Control
ICAP2 pin with the IEDG2 bit.
9
IC i R
INTCLK /CC[1:0]
Bits).
MS Byte
IC i HR
).
LS Byte
IC i LR
Table 22
– Set the ICIE bit to generate an interrupt after an
– Select the edge of the active transition on the
When an input capture occurs:
– ICF i bit is set.
– The IC i R register contains the value of the free
– A timer interrupt is generated if the ICIE bit is set
Clearing the Input Capture interrupt request is
done by:
1. Reading the SR register while the ICF i bit is set.
2. An access (read or write) to the IC i LR register.
Note: After reading the IC i HR register, transfer of
input capture data is inhibited until the IC i LR regis-
ter is also read.
The IC i R register always contains the free running
counter value which corresponds to the most re-
cent input capture.
input capture.
ICAP1 pin with the IEDG1 bit.
running counter on the active transition on the
ICAP i pin (see
and the ICIS bit (or EFTIS bit if only global inter-
rupt is available) is set. Otherwise, the interrupt
remains pending until both conditions become
true.
Figure
58).