GS84036AT-150I GSI TECHNOLOGY, GS84036AT-150I Datasheet

GS84036AT-150I

Manufacturer Part Number

GS84036AT-150I

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS84036AT-150I.pdf (31 pages)

Specifications of GS84036AT-150I

Density

4Mb

Access Time (max)

10ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

83.3MHz

Operating Supply Voltage (typ)

3.3V

Address Bus

17b

Package Type

TQFP

Operating Temp Range

-40C to 85C

Number Of Ports

Supply Current

175mA

Operating Supply Voltage (min)

3.135V

Operating Supply Voltage (max)

3.6V

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Number Of Words

128K

Lead Free Status / Rohs Status

Not Compliant

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TQFP, BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-bump BGA

• RoHS-compliant 100-lead TQFP and 119-bump BGA

Functional Description

Applications

The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS84018/32/36A is

available in a JEDEC standard 100-lead TQFP or 119-Bump

BGA package.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Rev: 1.19 10/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

packages

packages available

, E

256K x 18, 128K x 32, 128K x 36

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

, E

4Mb Sync Burst SRAMs

), address burst

tCycle

Parameter Synopsis

1/31

335 mA

210 mA

5.5 ns

3.0 ns

–180

8 ns

9 ns

310 mA

190 mA

6.0 ns

3.5 ns

8.5 ns

10 ns

–166

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin/bump (pin 14 in the TQFP and

bump 5R in the BGA). Holding the FT mode pin/bump low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipelined mode, activating the rising-edge-triggered

Data Output Register.

SCD Pipelined Reads

The GS84018/32/36A is an SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using byte write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS84018/32/36A operates on a 3.3 V power supply and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

280 mA

165 mA

6.6 ns

3.8 ns

10 ns

12 ns

–150

GS84018/32/36AT/B-180/166/150/100

DDQ

190 mA

135 mA

4.5 ns

10 ns

12 ns

15 ns

–100

) pins are used to de-couple output noise

180 MHz–100 MHz

3.3 V and 2.5 V I/O

3.3 V V

Related parts for GS84036AT-150I

GS84036AT-150I Summary of contents

Page 1

... KQ 3-1-1-1 I 335 mA 310 mA 280 mA DD Flow 8 Through tCycle 2-1-1-1 I 210 mA 190 mA 165 mA DD 1/31 GS84018/32/36AT/B-180/166/150/100 180 MHz–100 MHz 3 3.3 V and 2.5 V I/O ) pins are used to de-couple output noise DDQ –100 10 ns 4.5 ns 190 135 mA © 1999, GSI Technology DD ...

Page 2

... Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84018A 100-Pin TQFP Pinout (Package T) 256K x 18 Top View These pins can also be left floating 2/31 GS84018/32/36AT/B-180/166/150/100 DDQ DQP VDDQ VDD VDDQ VDDQ © 1999, GSI Technology ...

Page 3

... Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84032A 100-Pin TQFP Pinout (Package T) 128K x 32 Top View 3/31 GS84018/32/36AT/B-180/166/150/100 DDQ DDQ DDQ DDQ © 1999, GSI Technology ...

Page 4

... Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84036A 100-Pin TQFP Pinout (Package T) 128K x 36 Top View 4/31 GS84018/32/36AT/B-180/166/150/100 DQP DDQ DDQ DDQ DDQ DQP 51 A © 1999, GSI Technology ...

Page 5

... Data I/O Pin; Byte C 9th Data I/O Pin; Byte D Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect 5/31 © 1999, GSI Technology ...

Page 6

... GS84018A Pad Out—119-Bump BGA—Top View (Package Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ADSP DDQ ADSC DDQ ADV DDQ DDQ DQP LBO DDQ 6/31 GS84018/32/36AT/B-180/166/150/100 DDQ DQP DDQ DDQ DDQ DDQ © 1999, GSI Technology ...

Page 7

... GS84032A Pad Out—119-Bump BGA—Top View (Package Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ADSP DDQ ADSC DDQ ADV DDQ DDQ LBO DDQ 7/31 GS84018/32/36AT/B-180/166/150/100 DDQ DDQ DDQ DDQ DDQ © 1999, GSI Technology ...

Page 8

... T U Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ADSP DDQ ADSC DQP DDQ ADV DDQ DDQ DQP LBO DDQ 8/31 GS84018/32/36AT/B-180/166/150/100 DDQ DQP DDQ DDQ DDQ DQP DDQ © 1999, GSI Technology ...

Page 9

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84018/32/36AT/B-180/166/150/100 GS84018/32/36A Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 10/31 A Memory Array DQxn–DQxn © 1999, GSI Technology ...

Page 11

... Flow Through Pipeline Active ZZ Standby Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 11/31 GS84018/32/36AT/B-180/166/150/100 = I SB A[1:0] A[1:0] A[1:0] A[1: © 1999, GSI Technology ...

Page 12

... C D Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com may be used in any combination with BW to write single or multiple bytes. D 12/31 GS84018/32/36AT/B-180/166/150/100 B B Notes © 1999, GSI Technology ...

Page 13

... Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. State Diagram Key None X H None X L None Next CR X Next CR H Next CW X Next 13/31 GS84018/32/36AT/B-180/166/150/100 2 ADSP ADSC ADV © 1999, GSI Technology High-Z X High-Z X High ...

Page 14

... ADSP is tied high and ADV is tied low. Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write 14/31 GS84018/32/36AT/B-180/166/150/100 First Read Burst Read CR ) and Write ( and GW) control inputs © 1999, GSI Technology ...

Page 15

... Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 15/31 GS84018/32/36AT/B-180/166/150/100 First Read Burst Read CR © 1999, GSI Technology ...

Page 16

... DDn 16/31 GS84018/32/36AT/B-180/166/150/100 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 3.3 3.6 V 2.5 2.7 V © 1999, GSI Technology Unit Notes ...

Page 17

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Overshoot Measurement and Timing 17/31 Max. Unit Notes 0.3 V 1,3 DDQ 0 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° 50% tKC © 1999, GSI Technology ...

Page 18

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 18/31 GS84018/32/36AT/B-180/166/150/100 Typ. Max. Unit 30pF © 1999, GSI Technology ...

Page 19

... OUT DD = 2.375 V 1.7 V DDQ = 3.135 V 2.4 V DDQ = 8 mA — -150 -100 –40 0 – 85°C 70°C 85°C 70°C 320 280 290 190 200 165 175 135 © 1999, GSI Technology Max 100 — — 0.4 V –40 Unit to 85°C 200 mA 145 ...

Page 20

... GSI Technology Unit ...

Page 21

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 21/31 GS84018/32/36AT/B-180/166/150/100 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 1999, GSI Technology Deselect tKQX tHZ ...

Page 22

... Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 22/31 GS84018/32/36AT/B-180/166/150/100 Cont Deselected with E1 Q(C+1) Q(C+2) Q(C+3) Q(C) © 1999, GSI Technology Deselect tHZ tKQX ...

Page 23

... Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 23/31 GS84018/32/36AT/B-180/166/150/100 tZZR © 1999, GSI Technology ...

Page 24

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84018/32/36AT/B-180/166/150/100 θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 24/ © 1999, GSI Technology ...

Page 25

... Pin #1 Corner 0.70 REF 12.00 30 TYP. SEATING PLANE C Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84018/32/36AT/B-180/166/150/100 BOTTOM VIEW Ø0. Ø0. Ø0.60~0.90 (119x) Ø1.00(3x) REF 0.20(4x) 25/ 1.27 7.62 14±0.20 © 1999, GSI Technology ...

Page 26

... GS84032AT-180I 128K x 32 GS84032AT-166I 128K x 32 GS84032AT-150I 128K x 32 GS84032AT-100I 128K x 36 GS84036AT-180I 128K x 36 GS84036AT-166I 128K x 36 GS84036AT-150I 128K x 36 GS84036AT-100I 256K x 18 GS84018AGT-180 256K x 18 GS84018AGT-166 256K x 18 GS84018AGT-150 256K x 18 GS84018AGT-100 128K x 32 GS84032AGT-180 128K x 32 ...

Page 27

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.19 10/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 28

Page 29

Page 30

... Operating DD Content Currents table • Corrected incorrect package type in ordering information table Content • Removed 200 MHz references from entire datasheet Content • Updated format Content • Added 190 MHz speed bin 30/31 GS84018/32/36AT/B-180/166/150/100 © 1999, GSI Technology ...

Page 31

... BGA RoHS part, corrected incorrect temperature designator in ordering information table • Added note to TQFP pinouts (pg Content • Updated Power Supply Voltage Ranges table (pg. 16) • Updated Logic Level tables (pg. 17) • Removed 190 MHz speed bin Content 31/31 GS84018/32/36AT/B-180/166/150/100 © 1999, GSI Technology ...

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