CY14B104N-ZS45XCES Cypress Semiconductor Corp, CY14B104N-ZS45XCES Datasheet - Page 3

• Manufacturer Part Number: CY14B104N-ZS45XCES
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B104N-ZS45XCES

• Word Size: 16b
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Pin Count: 44
• Mounting: Surface Mount
• Supply Current: 50mA
• Lead Free Status / Rohs Status: Compliant

Pinouts
Pin Definitions
Document #: 001-07102 Rev. *I
DQ0 – DQ15
DQ0 – DQ7
Pin Name
A
A
0
0
V
BHE
HSB
BLE
V
V
WE
OE
NC
CE
– A
– A
CAP
CC
SS
18
17
(continued)
Power Supply Power Supply Inputs to the Device.
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
No Connect
IO Type
Ground
Input
Input
Input
Input
Input
Input
Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
operation.
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE HIGH.
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground for the Device. Must be connected to the ground of the system.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional).
nonvolatile elements.
No Connect. Do not connect this pin to the die.
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
V
WE
NC
NC
NC
NC
NC
CE
PRELIMINARY
CC
SS
A
A
A
A
A
A
A
A
A
A
[3]
0
1
2
3
4
5
6
7
8
9
1
10
11
12
13
14
15
16
17
18
19
25
26
27
2
3
4
5
6
7
8
9
20
21
22
23
24
54 - TSOP II
(
Top View
not to scale)
(x16)
Description
49
41
40
39
37
32
28
50
48
47
46
45
44
43
42
38
36
35
34
33
31
30
29
54
53
52
51
HSB
DQ15
NC
NC
A
OE
BHE
BLE
DQ14
DQ13
DQ12
NC
NC
A
A
V
DQ9
DQ8
V
A
A
A
A
A
V
DQ11
DQ10
17
16
15
12
11
10
SS
CAP
14
13
CC
[2]
CY14B104L, CY14B104N
Page 3 of 23
[+] Feedback