CY14B104N-ZS45XCES Cypress Semiconductor Corp, CY14B104N-ZS45XCES Datasheet - Page 10

• Manufacturer Part Number: CY14B104N-ZS45XCES
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B104N-ZS45XCES

• Word Size: 16b
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Pin Count: 44
• Mounting: Surface Mount
• Supply Current: 50mA
• Lead Free Status / Rohs Status: Compliant

AutoStore/Power Up RECALL
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.
Hardware STORE Cycle
Switching Waveforms
Notes
t
t
V
t
t
t
t
t
t
t
t
t
Parameters
15. t
16. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place.
17. The software sequence is clocked with CE controlled or OE controlled reads.
18. The six consecutive addresses must be read in the order listed in
19. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.
20. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command
21. On a hardware STORE initiation, SRAM operation continues to be enabled for time t
22. HSB must remain HIGH during READ and WRITE cycles.
HRECALL
STORE
VCCRISE
RC
AS
CW
GHAX
RECALL
SS
DELAY
HLHX
Document #: 001-07102 Rev. *I
SWITCH
Parameters
Parameters
[19, 20]
DQ (DATA OUT)
HRECALL
[21]
[16]
ADDRESS
[15]
starts from the time V
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Soft Sequence Processing Time
Time Allowed to Complete SRAM Cycle
Hardware STORE Pulse Width
Power Up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
Description
CC
rises above V
Figure 6. SRAM Read Cycle #1: Address Controlled
SWITCH.
t
OHA
Description
Description
t
AA
PRELIMINARY
Min
Table 1
15
12
0
1
15 ns
on page 5. WE must be HIGH during all six consecutive cycles.
Max
200
70
t
RC
DELAY
Min
20
15
0
1
to allow read and write cycles to complete.
20 ns
DATA VALID
Max
200
70
CY14B104L/CY14B104N
Min
150
Min
25
20
[11, 12, 22]
0
1
[17, 18]
25 ns
CY14B104L, CY14B104N
CY14B104L/CY14B104N
Min
15
Max
200
1
70
Max
2.65
20
15
Min
45
30
0
1
45 ns
Max
70
Max
200
70
Page 10 of 23
Unit
ms
ms
μs
V
Unit
Unit
ns
ns
ns
ns
μs
μs
μs
ns
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