DS90CF562MTDX National Semiconductor, DS90CF562MTDX Datasheet - Page 11

• Manufacturer Part Number: DS90CF562MTDX
• Manufacturer: National Semiconductor

Specifications of DS90CF562MTDX

• Number Of Elements: 3
• Number Of Receivers: 3
• Number Of Drivers: 21
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 5V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Output Type: Flat Panel Display
• Differential Output Voltage: 450mV
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TSSOP
• Lead Free Status / Rohs Status: Not Compliant

TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
CC
CC
DS90CF561 Pin Description—FPD Link Transmitter
DS90CF562 Pin Description—FPD Link Receiver
Pin Name
Pin Name
CC
CC
CC
CC
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
No.
No.
21
21
3
3
1
1
1
1
4
5
1
2
1
3
3
3
1
1
1
1
4
5
1
2
1
3
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE, FPFRAME,
DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The falling edge acts as data strobe.
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The falling edge acts as data strobe.
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
11
Description
Description
www.national.com