PEB24911HV13 Lantiq, PEB24911HV13 Datasheet - Page 44

• Manufacturer Part Number: PEB24911HV13
• Manufacturer: Lantiq

Specifications of PEB24911HV13

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.5
The U-transceiver has to synchronize onto an externally provided PTT-master clock. A
phase locked loop (PLL) is integrated in the AFE (PEF 24902) to generate the 15.36 MHz
system clock. A synchronized system clock guarantees that U-interface transmission will
be synchronous to the PTT-master clock.
The AFE is able to synchronize onto a 8 kHz or a 2048 kHz system clock. Infineon
recommends however to feed the FSC clock input of the DFE-Q V2.1 and the PLL
reference clock input (pin CLOCK) of the AFE from the same clock source. Please
refer to the PEF 24902 Data Sheet for further details on the PLL.
For the connection of the AFE clock output line with the DFE-Q V2.1 clock input line
(CL15) please refer to
3.6
The U-interface establishes the direct link between the exchange and the terminal side.
It consists of two copper wires. The Quad IEC AFE uses four differential outputs (AOUT,
BOUT) and four differential inputs (AIN, BIN) for transmission and reception. These
differential signals are coupled via four hybrids and four transformers to the four two-wire
U-interfaces. The nominal peak values of 3 correspond to a 3.2 Vpp chip output and 2.5
Vpp on the U-interface.
Direct access to the U-interface is not possible. 2B + D user data can be inserted and
extracted via the IOM
IOM
DFE-Q V2.1 itself and allow no external influence (e.g. CRC-checksum).
3.7
Transmission over the U
code used reduces two binary informations to one quaternary symbol (2B1Q) resulting
in a total bit rate of 160 kbit/s. 144 kbit/s are user data (B1 + B2 + D), 16 kbit/s are used
for maintenance and synchronization information.
Data is grouped together into U-superframes of 12 ms each. The beginning of a new
superframe is marked by an inverted synchronization word (ISW). Each superframe
consists of eight basic frames (1.5 ms) which begin with a standard synchronization word
(SW) and contain 222 bits of information. The structure of one U-superframe is illustrated
in
Figure 16
Data Sheet
ISW
<---
Figure 16
®
-2 monitor commands. The remaining maintenance bits are fully controlled by the
1. Basic Frame
Clock Generation
U-Transceiver Functions
2B1Q Frame Structure
and
U-Superframe Structure
Figure
®
Figure 5
-2 interface. Control of maintenance bits is partly provided via
2B1Q
17.
SW
-interface is performed at a symbol rate of 80 kBaud. The
and
2. Basic Frame
Figure
12 ms
34
6.
. . .
SW
Functional Description
8. Basic Frame
PEF 24911
2001-07-16
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