PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 43

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in
3.2.5
The ISAC-SX provides two timers which can be used for various purposes. Each of them
provides two modes
only once after expiration of the selected period, and a periodic timer interrupt, which
means an interrupt is generated continuously after every expiration of that period.
Table 7
Address
24
65
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from AUXI
(TIN1, TIN2) and each of the interrupt sources can be masked in AUXM.
Figure 10
Data Sheet
H
H
Timer Modes
Register
TIMR1
TIMR2
ISAC-SX Timers
Timer Interrupt Status Registers
TRAN
MASK
AUX
MOS
CIC
(Table
ICB
ICD
Interrupt
ST
7), a count down timer interrupt, i.e. an interrupt is generated
Modes
Periodic
Count Down
Periodic
Count Down
TRAN
ISTA
AUX
MOS
CIC
ICB
ICD
ST
43
AUXM
TIN2
TIN1
INT1
INT0
EAW
WOV
Description of Functional Blocks
Period
64 ... 2048 ms
64 ms ... 14.336 s
1 ... 63 ms
1 ... 63 ms
Figure
AUXI
TIN2
EAW
WOV
TIN1
INT1
INT0
9.
PEB 3086
2003-01-30
ISAC-SX