MAX1917EEE Maxim Integrated Products, MAX1917EEE Datasheet - Page 17

• Manufacturer Part Number: MAX1917EEE
• Description: Other Power Management
• Manufacturer: Maxim Integrated Products

Specifications of MAX1917EEE

• Case: ssop
• Dc: 03+
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than or
equal to I
design the circuit to tolerate:
where I
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. If short-circuit
protection without overload protection is enough, a nor-
mal I
nent stresses.
MAX1917 has on-chip MOSFETs drivers (DH and DL)
that dissipate the power loss due to driving the external
MOSFETs. Power dissipation due to a MOSFET driver is
given by:
where Q
high-side and low-side MOSFETs, respectively. Select
the switching frequency and V+ correctly to ensure the
power dissipation does not exceed the package power
dissipation requirement.
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all of the power components on the top
side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
1) Keep the high-current paths short, especially at the
2) Connect GND and PGND together as close to the
Controller for DDR Memory and Termination Supplies
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
IC as possible.
Tracking, Sinking and Sourcing, Synchronous Buck
I
LOAD
LOAD
LIMIT(HIGH)
GH
LOAD(MAX)
P
value can be used for calculating compo-
DR
= I
and Q
LIMIT(HIGH)
=
Applications Information
( )
V
Control IC Power Dissipation
______________________________________________________________________________________
+
GL
. To protect against this condition,
×
is the maximum valley current
are the total gate charge of the
(
f
S
+ (LIR / 2) (I
×
(
Q
GH
+
PC Board Layout
Q
GL
LOAD
)
+
I
(MAX))
VTTR
)
3) Keep the power traces and load connections short.
4) LX and PGND connections to Q2 for current limiting
5) When trade-offs in trace lengths must be made, it is
6) Ensure that the VTT feedback connection to C
7) VTT feedback sense point should also be as close
8) Route high-speed switching nodes away from sen-
9) Make all pin-strap control input connections (ILIM,
TRANSISTOR COUNT: 2708
PROCESS: BiCMOS
This practice is essential for high efficiency. The
use of thick copper PC boards (2oz vs. 1oz) can
enhance full-load efficiency by 1% or more.
Correctly routing PC board traces is a difficult task
that must be approached in terms of fractions of
centimeters, where a single mΩ of excess trace
resistance causes a measurable efficiency penalty.
must be made using Kelvin-sense connections in
order to guarantee the current-limit accuracy. With
8-pin SO MOSFETs, this is best done by routing
power to the MOSFETs from outside using the top
copper layer, while tying in PGND and LX inside
(underneath) the 8-pin SO package.
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
is short and direct. In some cases, it may be desir-
able to deliberately introduce some trace length
(droop resistance) between the FB inductor node
and the output filter capacitor.
as possible to the load connection.
sitive analog nodes (DDR, EN/HSD, REF, ILIM).
etc.) to GND or VL close to the chip, and do not
connect to PGND.
Chip Information
OUT
17