MAX1917EEE Maxim Integrated Products, MAX1917EEE Datasheet - Page 16

• Manufacturer Part Number: MAX1917EEE
• Description: Other Power Management
• Manufacturer: Maxim Integrated Products

Specifications of MAX1917EEE

• Case: ssop
• Dc: 03+
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
The actual microfarad capacitance value required
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
As a result, the capacitor is usually selected by ESR
and voltage rating rather than by capacitance value
(this is true of tantalums, OS-CONs, POSCAPs, and
other electrolytics).
The input capacitor must meet the ripple current
requirement (I
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their superior surge current
capacity:
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
half of the ripple current. For example:
where I
voltage divided by the R
MAX1917, the minimum current-limit threshold (100mV
default setting) is 50mV. Use the worst-case maximum
value for R
add some margin for the rise in R
ture. A good general rule is to allow 0.5% additional
resistance for each °C of temperature rise.
When adjusting the current limit, use a 1% tolerance
R
in the current-limit tolerance.
The droop resistor, R
inductor before the output capacitor, sets the droop
voltage, V
age at the maximum load current, including ripple, is
just above the lower limit of the output tolerance:
16
ILIM
I
LIMIT(LOW)
______________________________________________________________________________________
resistor to prevent a significant increase of errors
R
I
RMS
DRP
LIMIT(LOW)
DRP
DS(ON)
=
<
I
LOAD
. Choose R
RMS
V
> I
Setting the Voltage Positioning
OUT TYP
LOAD(MAX)
from the MOSFET Q2 data sheet, and
) imposed by the switching currents.
(
×
= minimum current-limit threshold




Input Capacitor Selection
Setting the Current Limit
DRP
)
V
−
DRP
OUT
V
I
OUT MAX
, in series with the output
OUT MIN
- (LIR / 2)
DS(ON)
×
such that the output volt-
(
(
(
V
V
IN
IN
DS(ON)
)
)
−
−
V
LOAD(MAX)
V
of Q2. For the
✕
OUT
RIPPLE
I
LOAD(MAX)
with tempera-
)




/2
minus
R
given by:
R
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
input voltage:
Generally, a small high-side MOSFET is desired in order
to reduce switching losses at high input voltages.
However, the R
power-dissipation limits often limits how small the
MOSFET can be. Again, the optimum occurs when the
switching (AC) losses equal the conduction (R
losses. Calculating the power dissipation in Q1 due to
switching losses is challenging because it must allow for
difficult-to-quantify factors that influence the turn-on and
turn-off times. These factors include the internal gate
resistance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The fol-
lowing switching loss calculation provides only a very
rough estimate and is no substitute for breadboard eval-
uation, preferably including a check using a thermocou-
ple mounted on Q1:
where C
and I
For the low-side MOSFET, Q2, the worst-case power
dissipation always occurs at maximum input voltage:
DRP
DRP
PD(Q2) = (1 - V
PD(Q1) = (V
PD SWITCHING
GATE
should be chosen to handle this power dissipation.
introduces some power dissipation, which is
(
RSS
is the peak gate-drive source/sink current.
PD(DRP) = R
is the reverse transfer capacitance of Q1
OUT
DS(ON)
OUT
/ V
)
MOSFET Power Dissipation
=
IN(MIN)
/ V
C
required to stay within package
RSS
IN(MAX)
DRP
×
)
✕
✕
V
IN MAX
I
(I
)
OUT(MAX) 2
(
LOAD 2
✕
I
GATE
I
LOAD 2
)
2
)
× ×
✕
f I
(R
✕
R
DS(ON)
LOAD
DS(ON)
DS(ON)
)
)