MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 202

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

Timing System
9.6.7 Output Compare 1 Mask Register
9.6.8 Output Compare 1 Data Register
Technical Data
202
Address: $000C
Address: $000D
OC1M specifies which bits of port A will respond to a successful
compare for output capture 1. The bits of the OC1M[7:3] register
correspond to PA[7:3].
OC1M[7:3] — Output Compare 1 Masks
Use this register in conjunction with OC1M to specify the data that is to
drive the affected pin of port A after a successful OC1 compare. When a
successful OC1 compare occurs, a data bit in OC1D is stored in the
corresponding bit of port A for each bit that is set in OC1M.
Reset:
Reset:
Read:
Read:
Write:
Write:
0 = OC1 is disabled at the corresponding PA pin.
1 = OC1 is enabled at the corresponding PA pin.
Figure 9-19. Output Compare 1 Mask Register (OC1M)
Figure 9-20. Output Compare 1 Data Register (OC1D)
OC1M7
OC1D7
Bit 7
Bit 7
0
0
OC1M6
OC1D6
Timing System
6
0
6
0
OC1M5
OC1D5
5
0
5
0
OC1M4
OC1D4
4
0
4
0
OC1M3
OC1D3
3
0
3
0
2
0
0
2
0
0
M68HC11K Family
1
0
0
1
0
0
MOTOROLA
Bit 0
Bit 0
0
0
0
0