ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 68

• Manufacturer Part Number: ICS1893Y-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893Y-10LFT

7.2.8 Duplex Mode (bit 0.8)
7.2.9 Collision Test (bit 0.7)
7.2.10 IEEE Reserved Bits (bits 0.6:0)
ICS1893Y-10 Rev F 1/20/04
This bit provides a means of controlling the ICS1893Y-10 Duplex Mode. Its operation depends on several
other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the
ICS1893Y-10 is configured for:
•
•
This bit controls the ICS1893Y-10 Collision Test function. When an STA sets bit 0.7 to logic:
•
•
The IEEE reserves these bits for future use. When an STA:
•
•
The ICS1893Y-10 uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1893Y-10, an STA must maintain the default value of these bits. Therefore, ICS recommends that
during any STA write operation, an STA write the default value to all reserved bits, even those bits that are
Read Only.
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893Y-10 isolates bit 0.8 and uses the
DPXSEL input pin to establish the Duplex mode for the ICS1893Y-10. In this Hardware mode:
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.8 depends on the
Auto-Negotiation Enable bit, 0.12. When the auto-negotiation process is:
Zero, the ICS1893Y-10 disables the collision detection circuitry for the Collision Test function. In this
case, the COL signal does not track the TXEN signal. (The default value for this bit is logic zero, that is,
disabled.)
One, as per the ISO/IEE 8802-3 standard, clause 22.2.4.1.9, the ICS1893Y-10 enables the collision
detection circuitry for the Collision Test function, even if the ICS1893Y-10 is in Loopback mode (that is,
bit 0.14 is set to 1). In this case, the Collision Test function tracks the Collision Detect signal (COL) in
response to the TXEN signal. The ICS1893Y-10 asserts the Collision signal (COL) within 512 bit times of
receiving an asserted TXEN signal, and it de-asserts COL within 4 bit times of the de-assertion of the
TXEN signal.
Reads a reserved bit, the ICS1893Y-10 returns a logic zero.
Writes to a reserved bit, it must use the default value specified in this data sheet.
– Bit 0.8 is undefined.
– The ICS1893Y-10 provides a Duplex Mode Status bit (in the QuickPoll Detailed Status Register, bit
– Enabled, the ICS1893Y-10 isolates bit 0.8 and relies upon the results of the auto-negotiation process
– Disabled, bit 0.8 determines the Duplex mode. Setting bit 0.8 to logic:
ICS1893Y-10 Data Sheet - Release
17.14), which always shows the setting of an active link.
to establish the duplex mode.
• Zero selects half-duplex operations.
• One selects full-duplex operations. (When the ICS1893Y-10 is operating in Loopback mode, it
isolates bit 0.8, which has no effect on the operation of the ICS1893Y-10.)
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
68
Chapter 7 Management Register Set
January, 2004