ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 110

• Manufacturer Part Number: ICS1893Y-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893Y-10LFT

ICS1893Y-10 Rev F 1/20/04
Table 8-4. Configuration Pins (Continued)
HW/SW
LOCK
LSTA
MII/SI
NOD/REP
REF_IN
REF_OUT
RESETn
Name
ICS1893Y-10 Data Sheet - Release
Pin
Number
Pin
23
27
21
19
53
52
18
1
Output
Output
Type
Input
Input
Input
Input
Input
Input
Pin
Copyright © 2004, Integrated Circuit Systems, Inc.
Hardware/Software (Select).
When the signal on this pin is logic:
(Stream Cipher) Lock (Acquired).
When the signal on this pin is logic:
Link Status.
This pin is used to report the status of the link segment. When the
signal on this pin is logic:
This pin is mapped according to the interface for which the
ICS1893Y-10 is mapped. For the:
Media Independent Interface / Stream Interface (Select).
This pin is used in combination with the 10/LP and 10/100SEL pins to
configure the ICS1893Y-10 MAC/Repeater Interface. When the signal
on this pin is logic:
Node/Repeater (Select).
This selection on this pin affects both the SQE test and the Carrier
Sense (CSR) signal. When the signal on this pin is logic:
(Frequency) Reference Input.
This pin is connected to a 25-MHz oscillator or crystal. For a tolerance,
see
(Frequency) Reference Output.
This pin is used with a crystal.
(System) Reset (Active Low).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low, this pin selects Hardware mode operations.
High, this pin selects Software mode operations.
Low, the ICS1893Y-10 does not have a lock on the data stream.
High, the ICS1893Y-10 has a lock on the data stream.
Low, there is no link established.
High, there is a link established.
Media Independent Interface (MII), the LSTA is mapped as LSTA.
100M Symbol Interface, the LSTA is mapped as SD.
10M Serial Interface, the LSTA is mapped as LSTA.
Link Pulse Interface, the LSTA is mapped as SD.
Low, this pin configures the MAC/Repeater Interface as a Media
Independent Interface.
High, this pin configures the MAC/Repeater Interface as a Stream
Interface.
Low, this pin enables the ICS1893Y-10 to default to node
operations.
High, this pin enables the ICS1893Y-10 to default to repeater
operations.
When the signal on this active-low pin is logic:
– Low, the ICS1893Y-10 is in hardware reset.
– High, the ICS1893Y-10 is operational.
For more information on hardware resets, see the following:
–
–
Section 9.5.1, “Timing for Clock Reference In (REF_IN)
Section 4.1.2.1, “Hardware Reset”
Section 9.5.18, “Reset: Hardware Reset and Power-Down”
All rights reserved.
110
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description
January, 2004
Pin”.