PIC18F4620-E/P Microchip Technology Inc., PIC18F4620-E/P Datasheet - Page 38

• Manufacturer Part Number: PIC18F4620-E/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-E/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2525/2620/4525/4620
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
T
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
FIGURE 3-3:
FIGURE 3-4:
DS39626B-page 36
IOBST
.
Note 1: Clock transition typically occurs within 2-4 T
Peripheral
Program
Counter
INTRC
OSC1
Clock
Clock
CPU
Note 1: T
CPU Clock
Multiplexer
PLL Clock
Peripheral
Program
INTOSC
Counter
Output
OSC1
Clock
2: Clock transition typically occurs within 2-4 T
Q1
SCS1:SCS0 bits changed
Q2
PC
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
OST
Q3
= 1024 T
Q4
Q1
OSC
Q1
1
; T
T
OST
PLL
(1)
2
PC
= 2 ms (approx). These intervals are not shown to scale.
Q2
Clock Transition
3
T
PLL (1)
OSTS bit set
Q3
OSC
PC + 2
(1)
n-1
Q4
.
OSC
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
n
.
Q1
1
Transition
2
Clock
n-1 n
(2)
Q2
PC + 2
Q3
Q2
Q4
 2004 Microchip Technology Inc.
Q3 Q4
Q1
Q1
PC + 4
Q2
PC + 4
Q2
Q3
Q3