PIC18F4620-E/P Microchip Technology Inc., PIC18F4620-E/P Datasheet - Page 265

• Manufacturer Part Number: PIC18F4620-E/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-E/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

23.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 23-5:
TABLE 23-3:
 2004 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
File Name
Program Verification and
Code Protection
®
devices.
(PIC18F2525/4525)
These bits are unimplemented in PIC18FX525 devices; maintain this bit set.
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
Unimplemented
Unimplemented
48 Kbytes
Boot Block
Read ‘0’s
Read ‘0’s
Block 0
Block 1
Block 2
SUMMARY OF CODE PROTECTION REGISTERS
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2525/2620/4525/4620
WRTD
Bit 7
CPD
—
—
—
—
(PIC18F2620/4620)
Unimplemented
EBTRB
WRTB
Bit 6
CPB
64 Kbytes
Boot Block
Read ‘0’s
—
—
—
Block 0
Block 1
Block 2
Block 3
PIC18F2525/2620/4525/4620
WRTC
Preliminary
Bit 5
—
—
—
—
—
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00B7FFh
00C000h
00FFFFh
010000h
1FFFFFh
Address
Range
Bit 4
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
—
—
—
—
—
—
EBTR3
WRT3
CP3
Bit 3
—
—
—
(Unimplemented Memory Space)
(1)
(1)
(1)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
EBTR2
WRT2
Bit 2
CP2
—
—
—
EBTR1
WRT1
Bit 1
CP1
DS39626B-page 263
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—