ICS1893Y-10 IDT, Integrated Device Technology Inc, ICS1893Y-10 Datasheet - Page 89

• Manufacturer Part Number: ICS1893Y-10
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893Y-10; 800-1934-5; ICS1893Y-10

7.11 Register 16: Extended Control Register
ICS1893Y-10 Rev F 1/20/04
Table 7-16
to customize the operations of the device.
Note:
1. For an explanation of acronyms used in
2. During any write operation to any bit in this register, the STA must write the default value to all
Table 7-16. Extended Control Register (register 16 [0x10])
† The default is the state of this pin at reset.
16.15
16.14
16.13
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
16.1
16.0
Bit
ICS1893Y-10 - Release
Reserved bits.
Command Override Write
enable
ICS reserved
ICS reserved
ICS reserved
ICS reserved
PHY Address Bit 4
PHY Address Bit 3
PHY Address Bit 2
PHY Address Bit 1
PHY Address Bit 0
Stream Cipher Test Mode Normal operation
ICS reserved
NRZ/NRZI encoding
Transmit invalid codes
ICS reserved
Stream Cipher disable
lists the bits for the Extended Control Register, which the ICS1893Y-10 provides to allow an STA
Definition
Copyright © 2004, Integrated Circuit Systems, Inc.
Disabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
Read unspecified
NRZ encoding
Disabled
Read unspecified
Stream Cipher enabled Stream Cipher disabled
Section 5.8, “Status
Section 5.8, “Status
Section 5.8, “Status
Section 5.8, “Status
Section 5.8, “Status
When Bit = 0
All rights reserved.
Table
89
7-16, see
Interface”.
Interface”.
Interface”.
Interface”.
Interface”.
Enabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Test mode
Read unspecified
NRZI encoding
Enabled
Read unspecified
Chapter 1, “Abbreviations and
When Bit = 1
Chapter 7 Management Register Set
RW/0
RW/0
RW/0
RW/0
RW/0
RW/0
cess
Ac-
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
SF
SC
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Acronyms”.
P4RD†
P0AC†
P3TD†
P1CL†
P2LI†
January, 2004
fault
De-
0
0
0
0
0
0
–
1
0
0
0
Hex
–
–
–
8