DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 20

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit
Name
Default
Bit 7: Jitter Attenuator Full Latched (JAFL). This latched status bit is set to one when the jitter attenuator buffer
is full. JAFL is cleared when the host processor writes a one to it and is not set again until the full condition clears
and the buffer becomes full again. When JAFL is set, it can cause a hardware interrupt to occur if the JAFIE
interrupt-enable bit in the
to zero.
Bit 6: Jitter Attenuator Empty Latched (JAEL). This latched status bit is set to one when the jitter attenuator
buffer is empty. JAEL is cleared when the host processor writes a one to it and is not set again until the empty
condition clears and the buffer becomes empty again. When JAEL is set, it can cause a hardware interrupt to occur
if the JAEIE interrupt-enable bit in the
JAEIE is set to zero.
Bit 5: Transmitter Driver Monitor Latched (TDML). This latched status bit is set to one when the TDM status bit
changes state (low to high or high to low). TDML is cleared when the host processor writes a one to it and is not set
again until TDM changes state again. When TDML is set, it can cause a hardware interrupt to occur if the TDMIE
interrupt-enable bit in the
set to zero.
Bit 4: PRBS Detector Output Latched (PRBSL). This latched status bit is set to one when the PRBS status bit
changes state (low to high or high to low). PRBSL is cleared when the host processor writes a one to it and is not
set again until PRBS changes state again. When PRBSL is set, it can cause a hardware interrupt to occur if the
PRBSIE interrupt-enable bit in the
PRBSIE is set to zero.
Bit 3: PRBS Detector Bit Error Latched (PBERL). This latched status bit is set to one when the PRBS detector is
in sync and a bit error has been detected. PBERL is cleared when the host processor writes a one to it and is not
set again until another bit error is detected. When PBERL is set, it can cause a hardware interrupt to occur if the
PBERIE interrupt-enable bit in the
PBERIE is set to zero.
Bit 2: Receiver Code Violation Latched (RCVL). This latched status bit is set to one when the RCV status bit in
the
RCV goes high again. When RCVL is set, it can cause a hardware interrupt to occur if the RCVIE interrupt-enable
bit in the
Bit 1: Receiver Loss-of-Clock Lock Latched (RLOLL). This latched status bit is set to one when the RLOL status
bit in the
one to it and is not set again until RLOL changes state again. When RLOLL is set, it can cause a hardware
interrupt to occur if the RLOLIE interrupt-enable bit in the
RLOLL is cleared or RLOLIE is set to zero.
Bit 0: Receiver Loss-of-Signal Latched (RLOSL). This latched status bit is set to one when the RLOS status bit
in the
one to it and is not set again until RLOS changes state again. When RLOSL is set, it can cause a hardware
interrupt to occur if the RLOSIE interrupt-enable bit in the
RLOSL is cleared or RLOSIE is set to zero.
SR
SR
register goes high. RCVL is cleared when the host processor writes a one to it and is not set again until
SRIE
SR
register changes state (low to high or high to low). RLOSL is cleared when the host processor writes a
register changes state (low to high or high to low). RLOLL is cleared when the host processor writes a
register is set to one. The interrupt is cleared when RCVL is cleared or RCVIE is set to zero.
JAFL
7
0
SRIE
SRIE
JAEL
6
0
register is set to one. The interrupt is cleared when JAFL is cleared or JAFIE is set
register is set to one. The interrupt is cleared when TDML is cleared or TDMIE is
SRLn
Status Register Latched
04h, 14h, 24h, 34h
SRIE
SRIE
SRIE
register is set to one. The interrupt is cleared when PRBSL is cleared or
register is set to one. The interrupt is cleared when PBERL is cleared or
TDML
5
0
register is set to one. The interrupt is cleared when JAEL is cleared or
PRBSL
20 of 71
4
0
SRIE
SRIE
register is set to one. The interrupt is cleared when
register is set to one. The interrupt is cleared when
PBERL
3
0
RCVL
2
0
RLOLL
1
0
RLOSL
0
0