DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 10

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. PIN DESCRIPTIONS
Table 6-A
that active in each of the three control interface modes. Section
interface modes.
Table 6-A. Global Pin Descriptions
Note: These pins are always active.
E3MCLK
STMCLK
T3MCLK
JTCLK
NAME
JTRST
JTDO
JTMS
TEST
JTDI
RST
HIZ
HW
V
V
DD
SS
through
TYPE
I/O
I/O
I/O
I
I
I
I
I
I
O
PU
PU
PU
PU
PU
PU
P
P
I
I
Table 6-C
T3 Master Clock. If a clock is applied to T3MCLK, it must be transmission-quality (±20ppm, low jitter).
When present, the T3MCLK signal serves as the DS3 master clock for the CDRs and jitter attenuators
of all LIUs configured for DS3 operation. If T3MCLK is held low, the clock adapter block synthesizes the
DS3 master clock from the clock applied to E3MCLK (first choice) or the clock applied to STMCLK
(second choice). If T3MCLK is held high, each LIU in DS3 mode uses its TCLK signal as its master
clock. If T3MCLK is held low but E3MCLK and STMCLK are not toggling, then each LIU in DS3 mode
uses its TCLK signal as its master clock. Pin is input-only in Hardware mode, input/output in CPU Bus
mode. See Section
E3 Master Clock. If a clock is applied to E3MCLK, it must be transmission-quality (±20ppm, low jitter).
When present, the E3MCLK signal serves as the E3 master clock for the CDRs and jitter attenuators of
all LIUs configured for E3 operation. If E3MCLK is held low, the clock adapter block synthesizes the E3
master clock from the clock applied to T3MCLK (first choice) or the clock applied to STMCLK (second
choice). If E3MCLK is held high, each LIU in E3 mode uses its TCLK signal as its master clock. If
E3MCLK is held low but T3MCLK and STMCLK are not toggling, then each LIU in E3 mode uses its
TCLK signal as its master clock. Pin is input-only in Hardware mode, input/output in CPU Bus mode.
See Section
STS-1 Master Clock. If a clock is applied to STMCLK, it must be transmission-quality (±20ppm, low
jitter). When present, the STMCLK signal serves as the STS-1 master clock for the CDRs and jitter
attenuators of all LIUs configured for STS-1 operation. If STMCLK is held low, the clock adapter block
synthesizes the STS-1 master clock from the clock applied to T3MCLK (first choice) or the clock
applied to E3MCLK (second choice). If STMCLK is held high, each LIU in STS-1 mode uses its TCLK
signal as its master clock. If STMCLK is held low but T3MCLK and E3MCLK are not toggling, then each
LIU in STS-1 mode uses its TCLK signal as its master clock. Pin is input-only in Hardware mode,
input/output in CPU Bus mode. See Section
High-Z Enable Input (Active Low, Open Drain, Internal 10kΩ Pullup to V
0 = tri-state all output pins (Note that the JTRST pin must be low.)
1 = normal operation
Hardware Mode Select
0 = CPU bus mode
1 = Hardware mode
See Section
JTAG IEEE 1149.1 Test Serial Clock. JTCLK shifts data into JTDI on the rising edge and out of JTDO
on the falling edge. If boundary scan is not used, JTCLK should be pulled high.
JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10kΩ Pullup). Test instructions and data are
clocked in on this pin on the rising edge of JTCLK. If boundary scan is not used, JTDI should be left
unconnected or pulled high.
JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions and data are clocked out on this pin on
the falling edge of JTCLK.
JTAG IEEE 1149.1 Test Reset (Internal 10kΩ Pullup to V
reset the test access port (TAP) controller. If boundary scan is not used, JTRST can be held low or
high.
JTAG IEEE 1149.1 Test Mode Select (Internal 10kΩ Pullup to V
edge of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If boundary
scan is not used, JTMS should be left unconnected or pulled high.
Reset Input (Active Low, Open Drain, Internal 10kΩ Pullup to V
reset is pulled low, the internal circuitry is reset and the internal registers (CPU bus mode) are forced to
their default values. The device is held in reset as long as RST is low. RST should be held low for at
least two master clock cycles. See Section
Factory Test Pin. Leave unconnected or wire high for normal operation.
Positive Supply. 3.3V ±5%. All V
Ground Reference. All V
list the pins that are always active.
12
5
for details.
for more information.
12
for more information.
SS
signals should be wired together.
DD
10 of 71
signals should be wired together.
13
12
FUNCTION
for more information.
Table 6-D
for more information.
18
shows pin assignments for all three control
through
DD
). This pin is used to asynchronously
DD
DD
Table 6-F
). This pin is sampled on the rising
). When this global asynchronous
DD
)
list the additional pins