PIC18F2620-I/SP Microchip Technology Inc., PIC18F2620-I/SP Datasheet - Page 295
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F2620-I/SP
Manufacturer Part Number
PIC18F2620-I/SP
Description
28 Pin, 64 KB Flash, 3968 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2620-ISP.pdf
(390 pages)
Specifications of PIC18F2620-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
25
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
64K Bytes
Ram Size
4K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2620-I/SP
Manufacturer:
MICROCHIP
Quantity:
560
- Current page: 295 of 390
- Download datasheet (8Mb)
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
After Instruction
Decode
W
Q1
=
1
Move Literal to W
MOVLW k
0
k
None
The eight-bit literal ‘k’ is loaded into W.
1
MOVLW
literal ‘k’
Read
0000
Q2
5Ah
k
W
255
1110
5Ah
Process
Data
Q3
kkkk
Write to W
PIC18F2525/2620/4525/4620
Q4
kkkk
Preliminary
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
Move W to f
MOVWF
0
a
(W)
None
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
MOVWF
Read
0110
Q2
4Fh
FFh
4Fh
4Fh
f
[0,1]
255
f
REG, 0
f {,a}
111a
Process
Data
Q3
DS39626B-page 293
95 (5Fh). See
ffff
register ‘f’
Write
Q4
ffff
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