PIC18F2620-I/SP Microchip Technology Inc., PIC18F2620-I/SP Datasheet - Page 280
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F2620-I/SP
Manufacturer Part Number
PIC18F2620-I/SP
Description
28 Pin, 64 KB Flash, 3968 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2620-ISP.pdf
(390 pages)
Specifications of PIC18F2620-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
25
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
64K Bytes
Ram Size
4K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2620-I/SP
Manufacturer:
MICROCHIP
Quantity:
560
- Current page: 280 of 390
- Download datasheet (8Mb)
PIC18F2525/2620/4525/4620
BNOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39626B-page 278
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If OVERFLOW =
If OVERFLOW =
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Overflow
BNOV
-128
if OVERFLOW bit is ‘0’
(PC) + 2 + 2n
None
If the OVERFLOW bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
n
127
0101
BNOV Jump
operation
Process
Process
Data
Data
PC
Q3
Q3
No
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn
Preliminary
BNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If ZERO
If ZERO
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Zero
BNZ
-128
if ZERO bit is ‘0’
(PC) + 2 + 2n
None
If the ZERO bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
2004 Microchip Technology Inc.
n
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
127
0001
BNZ
operation
Process
Process
Data
Data
PC
Q3
Q3
No
Jump
nnnn
Write to PC
operation
operation
Q4
No
Q4
No
nnnn
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