PIC18F4620-I/PT Microchip Technology Inc., PIC18F4620-I/PT Datasheet - Page 269

• Manufacturer Part Number: PIC18F4620-I/PT
• Description: 44 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

24.0
PIC18F2525/2620/4525/4620 devices incorporate the
standard set of 75 PIC18 core instructions, as well as an
extended set of 8 new instructions, for the optimization
of code that is recursive or that utilizes a software stack.
The extended set is discussed later in this section.
24.1
The standard PIC18 instruction set adds many
enhancements to the previous PICmicro
sets, while maintaining an easy migration from these
PICmicro instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The PIC18 instruction set summary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register designator ‘f’ specifies which file
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the opera-
tion is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
 2004 Microchip Technology Inc.
The file register (specified by ‘f’)
The destination of the result (specified by ‘d’)
The accessed memory (specified by ‘a’)
The file register (specified by ‘f’)
The bit in the file register (specified by ‘b’)
The accessed memory (specified by ‘a’)
INSTRUCTION SET SUMMARY
Standard Instruction Set
®
instruction
PIC18F2525/2620/4525/4620
Preliminary
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
• The desired FSR register to load the literal value
• No operand required
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
• The mode of the table read and table write
• No operand required
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure 24-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 24-2,
lists the standard instructions recognized by the
Microchip MPASM™ Assembler.
Section 24.1.1 “Standard Instruction Set” provides
a description of each instruction.
(specified by ‘k’)
into (specified by ‘f’)
(specified by ‘—’)
(specified by ‘s’)
instructions (specified by ‘m’)
(specified by ‘—’)
DS39626B-page 267