SCAN92LV090VEH/NOPB National Semiconductor, SCAN92LV090VEH/NOPB Datasheet - Page 7

• Manufacturer Part Number: SCAN92LV090VEH/NOPB
• Description: IC TXRX LVDS 9CH W/SCAN 64LQFP
• Manufacturer: National Semiconductor
• Series: SCANr
• Type: Transceiverr

Specifications of SCAN92LV090VEH/NOPB

• Number Of Drivers/receivers: 9/9
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *SCAN92LV090VEH; *SCAN92LV090VEH/NOPB; SCAN92LV090VEH

Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-1108, AN-977,
AN-971, and AN-903.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recommended
practices are:
•
•
•
•
•
•
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
•
Test Circuits and Timing Waveforms
Use at least 4 PCB board layer (Bus LVDS signals,
ground, power and TTL signals).
Keep drivers and receivers as close to the (Bus LVDS port
side) connector as possible.
Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Two or three high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel
should be used between each V
capacitors should be as close as possible to the V
Multiple vias should be used to connect V
planes to the pads of the by-pass capacitors.
In addition, randomly distributed by-pass capacitors
should be used.
Use the termination resistor which best matches the
differential impedance of your transmission line.
Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to <0.5 inches.
Isolate TTL signals from Bus LVDS signals
Use controlled impedance media. The backplane and
connectors should have a matched differential
impedance.
FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit
CC
and ground. The
FIGURE 1. Differential Driver DC Test Circuit
CC
and Ground
CC
pin.
7
X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
DE
H
H
H
L
LOOP BACK MODE
MODE SELECTED
RECEIVER MODE
TRI-STATE MODE
DRIVER MODE
RE
H
L
L
L
TABLE 2. Transmitter Mode
TABLE 1. Functional Table
INPUTS
0.8V< D
TABLE 3. Receiver Mode
−100 mV < V
INPUTS
H (> +100 mV)
L (< −100 mV)
(RI+) – (RI−)
D
10124204
H
X
L
IN
IN
<2.0V
mV
X
10124203
ID
< +100
DE
H
H
L
L
OUTPU
DO+
H
X
Z
OUTPUTS
L
H
X
T
L
Z
www.national.com
DO−
RE
H
X
H
H
L
Z
L
L