KSZ8041TL-S Micrel Inc, KSZ8041TL-S Datasheet - Page 26

IC TXRX PHY 10/100 BASE 48TQFP

KSZ8041TL-S

Manufacturer Part Number
KSZ8041TL-S
Description
IC TXRX PHY 10/100 BASE 48TQFP
Manufacturer
Micrel Inc
Type
Transceiverr
Datasheet

Specifications of KSZ8041TL-S

Number Of Drivers/receivers
1/1
Protocol
SMII
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
48-TQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-3626
KSZ8041TL-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8041TL-S
Manufacturer:
Micrel
Quantity:
374
Part Number:
KSZ8041TL-S
Manufacturer:
Micrel Inc
Quantity:
10 000
Micrel, Inc.
MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
December 2009
x
x
MII
Signal Name
TXC
TXEN
TXD[3:0]
RXC
RXDV
RXD[3:0]
RXER
CRS
COL
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
Direction
(with respect to PHY,
KSZ8041TL/FTL/MLL signal)
Output
Input
Input
Output
Output
Output
Output
Output
Output
Table 2. MII Signal Definition
Direction
(with respect to MAC)
Input
Output
Output
Input
Input
Input
Input, or (not required)
Input
Input
26
Description
Transmit Clock
(2.5 MHz for 10Mbps; 25 MHz for 100Mbps)
Transmit Enable
Transmit Data [3:0]
Receive Clock
(2.5 MHz for 10Mbps; 25 MHz for 100Mbps)
Receive Data Valid
Receive Data [3:0]
Receive Error
Carrier Sense
Collision Detection
KSZ8041TL/FTL/MLL
M9999-120909-1.2

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