DP83934CVUL-25 National Semiconductor, DP83934CVUL-25 Datasheet - Page 71

• Manufacturer Part Number: DP83934CVUL-25
• Description: IC CTRLR ORIENT NETWORK 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL-25

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934CVUL-25

7 0 Bus Interface
7 3 8 On-Chip Memory Arbiter
For applications which share the buffer memory area with
the
SONIC-T provides a fast on-chip memory arbiter for effi-
ciently resolving accesses between the SONIC-T and the
host system (Figure 7-23) The host system indicates its
intentions to use the shared-memory by asserting Memory
Request (MREQ) The SONIC-T will allow the host system
to use the shared memory by acknowledging the host sys-
tem’s request with Slave and Memory Acknowledge
SMACK Once SMACK is asserted the host system may
use the shared memory freely The host system gives up the
shared memory by deasserting MREQ
MREQ is clocked in on the falling edge of bus clock and is
double synchronized internally to the rising edge SMACK is
asserted on the falling edge of a Ts bus cycle If the
SONIC-T is not currently accessing the memory SMACK is
asserted immediately after MREQ was clocked in If howev-
er the SONIC-T is accessing the shared memory it finishes
its current memory transfer and then issues SMACK
SMACK will be asserted 1 or 5 bus clocks respectively
after MREQ is clocked in Since MREQ is double synchro-
nized it is not necessary to meet its setup time Meeting the
setup time for MREQ will however guarantee that SMACK
is asserted in the next or fifth bus clock after the current bus
clock SMACK will deassert within one bus clock after
MREQ is deasserted The SONIC-T will then finish its mas-
ter operation if it was using the bus previously
If the host system needs to access the SONIC-T’s registers
instead of shared memory CS would be asserted instead of
MREQ Accessing the SONIC-T’s registers works almost
exactly the same as accessing the shared memory except
that the SONIC-T goes into a slave cycle instead of going
idle See Section 7 3 7 for more information about how reg-
ister accesses work
Note 1 The successive assertion of CS and MREQ must be separated by
Note 2 The number of bus clocks between MREQ being asserted and the
Note 3 The way in which SMACK is asserted to due to CS is not the same
host
at least two bus clocks Both CS and MREQ must not be asserted
concurrently
assertion of SMACK when the SONIC-T is in Master Mode is 5 bus
clocks assuming there were no wait states in the Master Mode
access Wait states will increase the time for SMACK to go low by
the number of wait states in the cycle (the time will be 5
number of wait states)
as the way in which SMACK is asserted due to MREQ SMACK
goes low as a direct result of the assertion of MREQ whereas for
CS SAS must also be driven low (BMODE
0) before SMACK will be asserted This means that when SMACK
is asserted due to MREQ SMACK will remain asserted until MREQ
is deasserted Multiple memory accesses can be made to the
shared memory without SMACK ever going high When SMACK is
asserted due to CS however SMACK will only remain low as long
as SAS is also low (BMODE
will not remain low throughout multiple register accesses to the
SONIC-T because SAS must toggle for each register access This
is an important difference to consider when designing shared mem-
ory designs
system
(shared-memory
(Continued)
e
1) or high (BMODE
e
applications)
1) or high (BMODE
e
0) SMACK
a
the
the
e
71
7 3 9 Chip Reset
The SONIC-T has two reset modes a hardware reset and a
software reset The SONIC-T can be hardware reset by as-
serting the RESET pin or software reset by setting the RST
bit in the Command Register (Section 6 3 1) The two reset
modes are not interchangeable since each mode performs
a different function
After power-on the SONIC-T must be hardware reset be-
fore it will become operational This is done by asserting
RESET for a minimum of 10 transmit clocks (10 ethernet
transmit clock periods TXC) If the bus clock (BSCK) period
is greater than the transmit clock period RESET should be
asserted for 10 bus clocks instead of 10 transmit clocks A
hardware reset places the SONIC-T in the following state
(The registers affected are listed in parentheses See Table
7-3 and Section 6 3 for more specific information about the
registers and how they are affected by a hardware reset
Only those registers listed below and in Table 7-3 are affect-
ed by a hardware reset )
1
2
3
4
5
6
7
8
9
10 All interrupt status bits are reset (ISR)
11 The Extended Bus Mode is disabled (DCR)
12 HOLD will be asserted deasserted from the falling clock
during a hardware reset Bits 15–12 of the DCR2 are unknown until written
to All other bits in these two registers are unchanged
bits are unchanged
Bits 15 and 13 of the DCR and bits 4 through 0 of the DCR2 are reset to a 0
Bits LB1 LB0 and BRD are reset to a 0 during hardware reset All other
Command
Data Configuration
(DCR and DCR2)
Interrupt Mask
Interrupt Status
Transmit Control
Receive Control
End Of Buffer Count
Sequence Counters
CAM Enable
Receiver and Transmitter are disabled (CR)
The General Purpose timer is halted (CR)
All interrupts are masked out (IMR)
The NCRS and PTX status bits in the Transmit Control
Register (TCR) are set
The End Of Byte Count (EOBC) register is set to 02F8h
(760 words)
Packet and buffer sequence number counters are set to
zero
All CAM entries are disabled The broadcast address is
also disabled (CAM Enable Register and the RCR)
Loopback operation is disabled (RCR)
The latched bus retry is set to the unlatched mode
(DCR)
edge (DCR2)
TABLE 7-3 Internal Register Content after Reset
Register
Hardware
0094h
0000h
0000h
0101h
02F8h
0000h
0000h
Reset
Contents after Reset
0094h 00A4h
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
Software
Reset