DP83934CVUL-25 National Semiconductor, DP83934CVUL-25 Datasheet - Page 33

• Manufacturer Part Number: DP83934CVUL-25
• Description: IC CTRLR ORIENT NETWORK 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL-25

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934CVUL-25

Count Mismatch Excessive Collision or Excessive Deferral
5 0 Buffer Management
The SONIC-T performs a block operation of 6 3 or 2 ac-
cesses in the TDA depending on where the SONIC-T is in
the transmit process For the first fragment it reads the
TXpkt config to TXpkt frag size (6 accesses) For the next
fragment if any it reads the next 3 fields from TXpkt frag
ptr0 to TXpkt frag size (3 accesses) At the end of trans-
mission it writes the status information to TXpkt status and
reads the TXpkt link field (2 accesses)
5 5 3 2 Transmit Completion
The SONIC-T stops transmitting under two conditions In
the normal case the SONIC-T transmits the complete list of
descriptors in the TDA and stops after it detects EOL
In the second case certain transmit errors cause the
SONIC-T to abort transmission If FIFO Underrun Byte
(if enabled) errors occur transmission ceases The CTDA
register points to the last packet transmitted The system
can also halt transmission under software control by setting
the HTX bit in the Command register Transmission halts
after the SONIC-T writes to the TXpkt status field
5 5 4 Dynamically Adding TDA Descriptors
Descriptors can be dynamically added during transmission
without halting the SONIC-T The SONIC-T can also be
guaranteed to transmit the complete list including newly ap-
pended descriptors (barring any transmit abort conditions)
by observing the following rule The last TXpkt link field
must point to the next location where a descriptor will be
added (see step 3 below and Figure 5-16 )
The procedure for appending descriptors consists of
1 Creating a new descriptor with its TXpkt link pointing to
2 Resetting the EOL bit to a ‘‘0’’ of the previously last de-
3 Re-issuing the Transmit command (setting the TXP bit in
Step 3 assures that the SONIC-T will transmit all the pack-
ets in the list If the SONIC-T is currently transmitting the
Transmit command has no effect and continues transmitting
until it detects EOL
transmitting it continues transmitting from where it had pre-
viously stopped
the next vacant descriptor location and its EOL bit set to
a ‘‘1’’
scriptor
the Command register)
FIGURE 5-16 Initializing Last Link Field
e
1 If the SONIC-T had just finished
(Continued)
TL F 11719– 25
e
1
33
6 0 SONIC-T Registers
The SONIC-T contains two sets of registers The status
control registers and the CAM memory cells The status
control registers are used to configure control and monitor
SONIC-T operation They are directly addressable registers
and occupy 64 consecutive address locations in the system
memory space (selected by the RA5– RA0 address pins)
There are a total of 64 status control registers divided into
the following categories
User Registers These registers are accessed by the user
to configure control and monitor SONIC-T operation
These are the only SONIC-T registers the user needs to
access Figure 6-3 shows the programmer’s model and Ta-
ble 6-1 lists the attributes of each register
Internal Use Registers These registers (Table 6-2) are
used by the SONIC-T during normal operation and are not
intended to be accessed by the user
National Factory Test Registers These registers (Table
6-3) are for National factory use only and should never be
accessed by the user Accessing these registers during nor-
mal operation can cause improper functioning of the
SONIC-T
6 1 THE CAM UNIT
The CAM unit memory cells are indirectly accessed by pro-
gramming the CAM descriptor area in system memory and
issuing the LCAM command (setting the LCAM bit in the
Control register) The CAM cells do not occupy address lo-
cations in register space and thus are not accessible
through the RA5– RA0 address pins The CAM control regis-
ters however are part of the user register set and must be
initialized before issuing the LCAM command (see Section
6 3 10)
The Content Addressable Memory (CAM) consists of six-
teen 48-bit entries for complete address filtering (Figure 6-1)
of network packets Each entry corresponds to a 48-bit des-
tination address that is user programmable and can contain
any combination of Multicast or Physical addresses Each
entry is partitioned into three 16-bit CAM cells accessible
through CAM Address Ports (CAP2 CAP1 and CAP0) with
CAP0 corresponding to the least significant 16 bits of the
Destination Address and CAP2 corresponding to the most
significant bits The CAM is accessed in a two step process
First the CAM Entry Pointer is loaded to point to one of the
16 entries Then each of the CAM Address Ports is ac-
cessed to select the CAM cell The 16 user programmable
CAM entries can be masked out with the CAM Enable regis-
ter (see Section 6 3 10)
Note It is not necessary to program a broadcast address into the CAM
6 1 1 The Load CAM Command
Because the SONIC-T uses the CAM for a relatively long
period of time during reception it can only be written to via
the CAM Descriptor Area (CDA) and is only readable when
when it is desired to accept broadcast packets Instead to accept
broadcast packets set the BRD bit in the Receive Control register If
the BRD bit has been set the CAM is still active This means that it is
possible to accept broadcast packets at the same time as accepting
packets that match physical addresses in the CAM