FAN5019MTC Fairchild Semiconductor, FAN5019MTC Datasheet - Page 23

• Manufacturer Part Number: FAN5019MTC
• Description: DC/DC Switching Controllers PWM 4 phases contrlr
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5019MTC

• Number Of Outputs: 4
• Input Voltage: 10.2 V to 13.8 V
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C

PRODUCT SPECIFICATION
REV. 1.0.7 1/5/04
Typically, for main MOSFETs, one wants the highest
speed (low C
ON-resistance. One must select a device that meets the total
power dissipation (about 1.5 W for a single D-PAK) when
combining the switching and conduction losses.
For our example, we have selected a Fairchild FD6696 as the
main MOSFET (three total; n
(max) and R
Fairchild FDD6682 as the synchronous MOSFET (six total;
n
(max at T
than 3000 pF, satisfying that requirement. Solving for the
power dissipation per MOSFET at I
yields 1.24W for each synchronous MOSFET and 1.62W for
each main MOSFET. These numbers work well considering
there is usually more PCB area available for each main
MOSFET versus each synchronous MOSFET.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
the MOSFETs and is given by the following, where Q
the total gate charge for each main MOSFET and Q
total gate charge for each synchronous MOSFET:
Also shown is the standby dissipation factor (I
V
tion should be less than 400 mW. For our example, with
I
we find 202 mW in each driver, which is below the 400 mW
dissipation limit. See the FAN5009 data sheet for more
details.
Ramp Resistor Selection
The ramp resistor (R
internal PWM ramp. The value of this resistor is chosen to
provide the best combination of thermal balance, stability,
and transient response. The following expression is used for
determining the optimum value:
where A
current balancing amplifier gain, R
MOSFET ON-resistance, and C
capacitor value. A close standard 1% resistor value is 301k .
The internal ramp voltage magnitude can be calculated
using:
R
P
R
CC
SF
DRV
CC
R
R
= 6), with C
= 7 mA, Q
) for the driver. For the FAN5009, the maximum dissipa-
3
3
R
2
5
A
J
f
0
is the internal ramp amplifier gain, A
SW
D
= 125ºC). The synchronous MOSFET C
2 .
A
n
. 5
DS(MF)
R
ISS
95
R
GMF
650
) device, but these usually have higher
DS
iss
n
L
m
MF
nH
= 2880pF (max) and R
= 15m (max at T
= 24nC (max) and Q
C
R
5
Q
) is used for setting the size of the
R
pF
GMF
291
MF
n
SF
R
k
= 3), with a C
is the internal ramp
Q
DS
O
J
GSF
= 65A and I
= 125ºC) and an
is the total low-side
GSF
DS(SF)
I
CC
= 31nC (max),
CC
iss
D
= 11.9m
V
is the
times the
= 2058 pF
R
CC
GSF
iss
= 8.86A
GMF
is less
G
is the
(19)
(18)
for
is
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and transient response will
improve, but thermal balance will degrade. Likewise, if the
ramp is made smaller, thermal balance will improve at the
sacrifice of transient response and stability. The factor of
three in the denominator of equation 19 sets a ramp size that
gives an optimal balance for good stability, transient
response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input.
For this example, the overall ramp signal is found to be
0.974V.
Current Limit Set Point
To select the current limit set point, we need to find the
resistor value for R
FAN5019 is set with a 3V source (V
a gain of 10.4mV/mA (A
following:
For values of R
be lower than expected, so some adjustment of R
needed. Here, I
of the supply. For our example, choosing 120A for I
find R
nearest 1% value.
The per phase current limit described earlier has its limit
determined by the following:
For the FAN5019, the maximum COMP voltage
(V
is 1.2V, and the current balancing amplifier gain (A
Using V
ON-resistance at 125°C), we find a per-phase limit of 40.44A.
V
R
I
V
V
PHLIM
RT
LIM
R
R
COMP(MAX)
A
301
LIM
0
R
R
1
A
2 .
R
I
V
R
LIM
k
LIM
COMP
of 0.765V, and R
to be 200k , for which we chose 200k as the
1
n
C
1
2
A
R
V
) is 3.3 V, the COMP pin bias voltage (V
D
(
5
R
LIM
D
f
MAX
LIM
. 0
LIM
SW
pF
O
V
1
f
125
SW
R
)
R
V
LIM
greater than 500k , the current limit may
is the average current limit for the output
VID
DS
n
C
V
228
(
X
. The current limit threshold for the
MAX
R
1
D
5 .
LIM
kHz
R
)
V
V
DS(MAX)
O
BIAS
). R
. 0
LIM
I
765
2
R
LIM
of 5.95m (low-side
can be found using the
V
) across R
LIM
LIM
D
FAN5019
LIM
) is 5.
may be
with
BIAS
(23)
(21)
(20)
(22)
, we
23
)