MAX5945EAX+ Maxim Integrated Products, MAX5945EAX+ Datasheet - Page 23

• Manufacturer Part Number: MAX5945EAX+
• Description: IC NETWORK PWR CTRL 36-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5945EAX+

• Controller Type: Network Power Controller
• Interface: I²C
• Voltage - Supply: 3.3V
• Current - Supply: 4.2mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Interrupt Register
Table 6. Interrupt Mask Register
TSTR_FLT
IMAX_FLT
SYMBOL
DET_END
SYMBOL
SUP_FLT
LD_DISC
CL_END
MASK7
MASK6
MASK5
MASK4
MASK3
MASK2
MASK1
MASK0
PG_INT
PE_INT
ADDRESS = 01h
ADDRESS = 00h
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
______________________________________________________________________________________
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Interrupt mask bit 7. A logic high enables the SUP_FLT interrupts. A logic low disables the SUP_FLT
interrupts.
Interrupt mask bit 6. A logic high enables the TSTR_FLT interrupts. A low disables the TSTR_FLT
interrupts.
Interrupt mask bit 5. A logic high enables the IMAX_FLT interrupts. A logic low disables the
IMAX_FLT interrupts.
Interrupt mask bit 4. A logic high enables the CL_END interrupts. A logic low disables the CL_END
interrupts.
Interrupt mask bit 3. A logic high enables the DET_END interrupts. A logic low disables the
DET_END interrupts.
Interrupt mask bit 2. A logic high enables the LD_DISC interrupts. A logic low disables the LD_DISC
interrupts.
Interrupt mask bit 1. A logic high enables the PG_INT interrupts. A logic low disables the PG_INT
interrupts.
Interrupt mask bit 0. A logic high enables the PEN_INT interrupts. A logic low disables the PEN_INT
interrupts.
Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh
(Table 8).
Interrupt signal for startup failures. TSRT_FLT is the logic OR of bits [7:0] in register R08h/R09h
(Table 7).
Interrupt signal for current-limit violations. IMAX_FLT is the logic OR of bits [3:0] in register
R06h/R07h (Table 6).
Interrupt signal for completion of classification. CL_END is the logic OR of bits [7:4] in register
R04h/R05h (Table 5)
Interrupt signal for completion of detection. DET_END is the logic OR of bits [3:0] in register
R04h/R05h (Table 5).
Interrupt signal for load disconnection. LD_DISC is the logic OR of bits [7:4] in register R06h/R07h
(Table 6).
Interrupt signal for PGOOD status change. PG_INT is the logic OR of bits [7:4] in register R02h/R03h
(Table 4).
Interrupt signal for power-enable status change. PEN_INT is the logic OR of bits [3:0] in register
R02h/R03h (Table 4).
Quad Network Power Controller
DESCRIPTION
DESCRIPTION
for Power-Over-LAN
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