Z16C3220FSG Zilog, Z16C3220FSG Datasheet
Z16C3220FSG
Specifications of Z16C3220FSG
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Z16C3220FSG Summary of contents
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Z ILOG FEATURES Two Full-Capacity 20 MHz DMA Channels, Each with 32-Bit Addressing and 16-Bit Data Transfers. DMA Modes Include Single Buffer, Pipelined, Array- Chained and Linked-Array Chained. Ring Buffer Feature Supports Circular Queue of Buffers in Memory. Linked Frame ...
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... The CPU bus interface is designed for use with any conventional multiplexed or non-multiplexed bus from manufacturers of CISC and RISC processors including Intel, Motorola, and Zilog. The bus interface is configurable for 16-bit data, 8-bit data with separate address or 8-bit data without separate address to support multiplexed or non-multiplexed busses ...
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Z ILOG 16-Bit Internal Data Bus Host Bus Processor Interface Transmit DMA Transmit Time Slot Assigner PS97USC0200 Interrupt Control FIFO Serial Clock Logic DPLL Transmitter Counters BRG0, BRG1 Figure ...
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Z ILOG GENERAL DESCRIPTION (Continued) Address/ Data Bus Bus Timing Control Interrupt Ground TxD AD0 RxD AD1 /TxC AD2 /RxC AD3 /CTS AD4 /DCD AD5 /RxREQ AD6 /ABORT ...
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/UAS /INTACK R/W /WR /RD /DS /AS VCC VCC NC /RESET /CS D//C S//D /Wait//RDY 80 B// QFP 80 - Pin Figure 3. QFP 80-Pin Assignments P ...
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Z ILOG /ABORT /INT IEI IEO GND VCC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND VCC /RxREQ Figure 4. Z16C32 68-Pin PLCC Pin Assignments PIN DESCRIPTION Figure 2 shows the logical pin groupings of the IUSC’s pins, and ...
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Z ILOG Any Transaction and Including BCR Write Non- Multiplexed Bus BCR Write Transaction BCR[2]=0 BCR[2]=0 BCR[15]=1 BCR[15]=0 8-Bit With 8-Bit Without Separate Separate Address Address Note: The presence of one transaction with an /AS active between ...
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... S//D input during the initial BCR write. If S//D is High when the BCR is written, this line operates as a Ready/Wait line for Zilog and most Intel processors. In this mode, the IUSC will not complete a master cycle while this line is Low, and it asserts this line Low until it’s ready to complete an interrupt acknowledge cycle ...
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Z ILOG PIN DESCRIPTION (Continued) /BUSREQ Bus Request (output, active Low). The DMA controller section drives this line Low to request control of the host bus. /BUSREQ can be an open-drain or totem- pole output depending on a bit in ...
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Z ILOG PORT7/TxCOMPLT General-Purpose I/O or Transmit Com- plete (input or output). Software can program the IUSC so that this pin is a general-purpose input or output that it carries a Transmit Complete signal from the Transmitter, that ...
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Z ILOG DMA AND BUS INTERFACE CAPABILITIES The IUSC’s two versatile DMA channels combined with a flexible bus interface gives it the ability to meet a wide variety of application requirements. The time required to move data into and out ...
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... The interrupt subsystem of the IUSC derives from Zilog’s experience in providing the most advanced interrupt ca- pabilities in the microprocessor field. These capabilities are at their best when used with a Zilog microprocessor, but it is easy to interface the IUSC to work well with other microprocessors as well. Four pins are dedicated to create an interrupt daisy-chain hierarchy within the Serial Chan- nel and between the Serial Channel and the DMA ...
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Z ILOG DMA AND BUS INTERFACE CAPABILITIES (Continued) There are six sources of Receive Status interrupt. Each one is individually armed: Receiver exited hunt, received idle line, received break/abort, received code violation/end-of- transmission/end-of-message, parity error/abort and over- run error. The ...
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Z ILOG Buffer 1 Address Buffer 1 Length Buffer 1 RSBR or 0 Buffer 1 RSHR Link Address of Entry2 Figure 5. Linked List Mode with Linked Frame Status Transfer and Ring Buffer Features Another method by ...
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Z ILOG DATA COMMUNICATIONS CAPABILITIES The IUSC provides a full-duplex channel programmable for use in any common data communication protocol. The receiver and transmitter are completely independent and each is supported by a 32-byte deep FIFO and a 16-bit frame ...
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Z ILOG Transparent Bisync Mode. In this mode, the synchroni- zation pattern is DLE-SYN, programmable selected from either ASCII or EBCDIC encoding. The receiver recog- nizes control character sequences and automatically handles CRC calculations without CPU intervention. The transmitter is ...
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Z ILOG DATA COMMUNICATIONS CAPABILITIES (Continued) Character Counters The IUSC contains separate 16-bit character counters for the receiver and transmitter. The receive character counter is set to a programmable starting value or automatically at the beginning of each received frame ...
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Z ILOG Clock Multiplexers The clock multiplexer logic selects the receive and trans- mit clocks and optional outputs on the /RxC and/or /TxC pin(s). In the Z16C32, the PORT0 and PORT1 pins can be used directly as receive and transmit ...
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Z ILOG PROGRAMMING An Electronic Programmer’s Manual (MS DOS based) and a Technical Manual are available to provide details about programming the IUSC. Also included are explanations and features of all registers in the IUSC. The registers in the IUSC ...
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Z ILOG Any Transaction and Including BCR Write Non- Multiplexed Bus BCR Write Transaction BCR[2]=0 BCR[2]=0 BCR[15]=1 BCR[15]=0 8-Bit With 8-Bit Without Separate Separate Address Address Note: The presence of one transaction with an /AS active between ...
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Z ILOG PROGRAMMING (Continued) S//D D// ...
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Z ILOG S//D D// ...
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Z ILOG REGISTER DESCRIPTION This section describes the function of the various bits in the registers of the device. Throughout this section the follow- ing conventions are discussed: Control bits are written and read by the CPU and are not ...
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Z ILOG ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00001 Auto Modes Disabled 0 1 Buffered 1 0 Array Chained 1 1 Linked-Array Chained Figure 10. Tx/Rx DMA Mode Register (TDMR) (RDMR) 25 ...
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Z ILOG ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00011 (Shared Channel Channel 1 0 Alternating 1 1 Reserved ...
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Z ILOG Big End Array (16-Bit bus) AD15 Address n 31 Address n+2 15 Little End Array (16-Bit bus) AD15 Address n 15 Address n+2 31 Big End Array (8-Bit bus) AD7 Address n 31 Address n+1 23 Address n+2 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00100 (Shared) Figure 14a. DMA Array Count Register (DACR ...
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Z ILOG Address: 01001 (Shared) Figure 15. Burst Dwell Control Register (BDCR) Notes: BDCR Controls the amount of time that DMA may remain bus master. Bits 15 through 8 are used to select a limit for the number of DMA ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 01010 (Shared) Figure 16. DMA Interrupt Vector Register (DIVR) Address: 01100 (Shared) Figure 17. DMA Interrupt Control Register (DICR None ...
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Z ILOG Address: 01101 (Shared) Figure 18. Clear DMA Interrupt Register (CDIR) Address: 01110 (Shared) Figure 19. Set DMA Interrupt Register (SDIR) * Address: 01111 Figure 20. Tx/Rx DMA Interrupt Arm (TDIAR)/(RDIAR) Notes: * The format of this register is ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 10101 Figure 21. Tx/Rx Byte Count Register (TBCR)/(RBCR) Address: 10110 Figure 22. Tx/Rx Address Register (lower) (TARL)/(RARL Z16C32 IUSC ™ ...
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Z ILOG Address: 10111 Figure 23. Tx/Rx Address Register (Upper) (TARU)/(RARU) Address: 11101 Figure 24. Next Tx/Rx Byte Counter Register (NTBCR)/(RTBCR) PS97USC0200 Z16C32 IUSC ™ TAR <16> ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 11110 Figure 25. Next Tx/Rx Address Register (Lower) (NTARL)/(RTARL) Address: 11111 Figure 26. Next Tx/Rx Address Register (Upper) (NTARU)/(RTARU Z16C32 ...
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Z ILOG Base Address Base Address + 2 Base Address + 4 Base Address + 6 Base Address + 8 Base Address + 10 Base Address + 12 Base Address + 14 Base Address + 16 Last Base Address Last ...
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Z ILOG CONTROL REGISTERS (Continued) Base Address Base Address + 2 Base Address + 4 Base Address + 6 Base Address + 8 Base Address + 10 Base Address + 12 Base Address + 14 Base Address + 16 Base ...
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Z ILOG Base Address Base Address + 2 Base Address + 4 Base Address + 6 Base Address + 8 Base Address + 10 Base Address + 12 Base Address + 14 Base Address + 16 Last Base Address Last ...
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Z ILOG CONTROL REGISTERS (Continued) Base Address Base Address + 1 Base Address + 2 Base Address + 3 Base Address + 4 Base Address + 5 Base Address + 6 Base Address + 7 Base Address + 8 Base ...
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Z ILOG Base Address Base Address + 1 Base Address + 2 Base Address + 3 Base Address + 4 Base Address + 5 Base Address + 6 Base Address + 7 Base Address + 8 Base Address + 9 ...
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Z ILOG CONTROL REGISTERS (Continued) Base Address Base Address + 1 Base Address + 2 Base Address + 3 Base Address + 4 Base Address + 5 Base Address + 6 Base Address + 7 Base Address + 8 Base ...
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Z ILOG Base Address Base Address + 2 Base Address + 4 Base Address + 6 Base Address + 8 #2 Base Address #2 Base Address + 2 #2 Base Address + 4 #2 Base Address + 6 #2 Base ...
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Z ILOG CONTROL REGISTERS (Continued) Base Address Base Address + 2 Base Address + 4 Base Address + 6 Base Address + 8 Base Address + 10 Base Address + 12 Base Address + 14 #2 Base Address #2 Base ...
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Z ILOG Base Address Base Address + 2 Base Address + 4 Base Address + 6 Base Address + 8 #2 Base Address #2 Base Address + 2 #2 Base Address + 4 #2 Base Address + 6 #2 Base ...
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Z ILOG CONTROL REGISTERS (Continued) Base Address Base Address + 1 Base Address + 2 Base Address + 3 Base Address + 4 Base Address + 5 Base Address + 6 Base Address + 7 Base Address + 8 Base ...
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Z ILOG Base Address Base Address + 1 Base Address + 2 Base Address + 3 Base Address + 4 Base Address + 5 Base Address + 6 Base Address + 7 Base Address + 8 Base Address + 9 ...
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Z ILOG CONTROL REGISTERS (Continued) Base Address Base Address + 1 Base Address + 2 Base Address + 3 Base Address + 4 Base Address + 5 Base Address + 6 Base Address + 7 Base Address + 8 Base ...
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Z ILOG Address: 00000 D15 D14 D13 D12 D11 D10 Null Command Reserved Reset Highest IUS Reserved ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00001 D15 D14 D13 D12 D11 D10 ...
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Z ILOG Address: 00001 D15 D14 D13 D12 D11 D10 16X Data Rate 0 1 32X Data Rate 1 0 64X Data Rate 1 1 Reserved 0 0 One Stop Bit 0 1 Two Stop ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00001 D15 D14 D13 D12 D11 D10 Figure 39. Channel Mode Register, Isochronous Mode Address: 00001 D15 D14 D13 D12 D11 D10 One Stop Bit 0 ...
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Z ILOG Address: 00001 D15 D14 D13 D12 D11 D10 Figure 41. Channel Mode Register, Monosync Mode Address: 00001 D15 D14 D13 D12 D11 D10 SYN1 0 1 SYN0/SYN1 1 0 CRC/SYN1 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00001 D15 D14 D13 D12 D11 D10 Abort 0 1 Extended Abort 1 0 Flag 1 1 CRC/Flag Figure 43. Channel Mode Register, HDLC Mode Address: 00001 D15 D14 ...
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Z ILOG Address: 00001 D15 D14 D13 D12 D11 D10 16X Data Rate 0 1 32X Data Rate 1 0 64X Data Rate 1 1 Reserved Figure 45. Channel Mode Register, NBIP Mode Address: 00001 D15 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00001 D15 D14 D13 D12 D11 D10 Figure 47. Channel Mode Register, Slaved Monosync Mode Address: 00001 D15 D14 D13 D12 D11 D10 Abort 0 1 Extended ...
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Z ILOG Address: 00010 D15 D14 D13 D12 D11 D10 Figure 49. Channel Command/Status Register (CCSR) PS97USC0200 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00011 D15 D14 D13 D12 D11 D10 Status Block 0 1 One Word Status Block 1 0 Two Word Status Block 1 ...
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Z ILOG Address: 00100 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 51. Port Status Register (PSR) Z16C32 IUSC D0 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00101 D15 D14 D13 D12 D11 D10 Tri-State Output 0 1 Frame Sync Input 1 0 Output Output Tri-State Output 0 1 ...
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Z ILOG Address: 00110 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 53. Test Mode Data Register (TMDR Test ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 00111 D15 D14 D13 D12 D11 D10 D9 Figure 54. Test Mode Control Register (TMCR) Note: When software writes the value 1F to the LS byte of the Test Mode Control Register (TMCR), and ...
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Z ILOG Address: 01000 D15 D14 D13 D12 D11 D10 Disabled 0 1 Port0 Pin 1 0 /RxC Pin 1 1 /TxC Pin 0 0 Disabled 0 1 Port1 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 01001 D15 D14 D13 D12 D11 D10 32x Clock Mode 0 1 16x Clock Mode Clock Mode 1 1 Reserved 0 0 32x Clock ...
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Z ILOG Address: 01010 D15 D14 D13 D12 D11 D10 PS97USC0200 None ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 01011 D15 D14 D13 D12 D11 D10 /DCD Input 0 1 /DCD//SYNC Input 1 0 Output Output ...
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Z ILOG Address: 01100 D15 D14 D13 D12 D11 D10 PS97USC0200 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 01101 D15 D14 D13 D12 D11 D10 Null Command 0 1 Null Command 1 0 Reset IUS 1 1 Set IUS Figure 60. Daisy-Chain Control Register (DCCR ...
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Z ILOG Address: 01110 D15 D14 D13 D12 D11 D10 D9 Figure 61. Miscellaneous Interrupt Status Register (MISR) PS97USC0200 Z16C32 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 01111 D15 D14 D13 D12 D11 D10 Disabled 0 1 Rising Edge Only 1 0 Falling Edge Only 1 1 Both Edges Figure ...
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Z ILOG Address: 1x000 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 63. Receive Data Register (RDR) Z16C32 IUSC D1 D0 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 10001 D15 D14 D13 D12 D11 D10 CRC-CCITT 0 1 CRC- CRC- Reserved NRZ NRZB NRZI-Mark 0 1 ...
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Z ILOG Address: 10010 D15 D14 D13 D12 D11 D10 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 10011 D15 D14 D13 D12 D11 D10 Figure 66a. Receive Interrupt Control Register (RICR) Address: 10011 D15 D14 D13 D12 D11 D10 D9 Figure 66b. Receive Interrupt Control Register (RICR ...
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Z ILOG Address: 10011 D15 D14 D13 D12 D11 D10 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 10100 D15 D14 D13 D12 D11 D10 Figure 67. Receive Sync Register (RSR) Z16C32 IUSC ...
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Z ILOG Address: 10101 D15 D14 D13 D12 D11 D10 D9 Figure 68. Receive Count Limit Register (RCLR) PS97USC0200 Z16C32 IUSC ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 10110 D15 D14 D13 D12 D11 D10 D9 Figure 69. Receive Character Count Register (RCCR ...
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Z ILOG Address: 10111 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 70. Time Constant 0 Register (TC0R) Z16C32 IUSC ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 1x000 D15 D14 D13 D12 D11 D10 Figure 71. Transmit Data Register (TDR) Z16C32 IUSC ...
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Z ILOG Address: 11001 D15 D14 D13 D12 D11 D10 CRC-CCITT 0 1 CRC- CRC- Reserved NRZ NRZB NRZI-Mark NRZI-Space 1 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 11010 D15 D14 D13 D12 D11 D10 Null Command Reserved Preset CRC Reserved ...
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Z ILOG Address: 11011 D15 D14 D13 D12 D11 D10 D9 Figure 74a. Transmit Interrupt Control Register (TICR) Address: 11011 D15 D14 D13 D12 D11 D10 D9 Figure 74b. Transmit Interrupt Control Register (TICR) PS97USC0200 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 11011 D15 D14 D13 D12 D11 D10 ...
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Z ILOG Address: 11100 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 75. Transmit Sync Register (TSR) Z16C32 IUSC D1 D0 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 11101 D15 D14 D13 D12 D11 D10 D9 Figure 76. Transmit Count Limit Register (TCLR ...
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Z ILOG Address: 11110 D15 D14 D13 D12 D11 D10 D9 Figure 77. Transmit Character Count Register (TCCR) PS97USC0200 Z16C32 IUSC ...
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Z ILOG CONTROL REGISTERS (Continued) Address: 11111 D15 D14 D13 D12 D11 D10 Figure 78. Time Constant 1 Register (TC1R ...
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Z ILOG Address: None * D15 D14 D13 D12 D11 D10 Refer to Figure 22 (Channel Control Register) * Bits 6-7 for Access Method Figure 79. Receive Status Block Register (RSBR) PS97USC0200 ...
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Z ILOG CONTROL REGISTERS (Continued) Address: None * D15 D14 D13 D12 D11 D10 D9 Refer to Figure 22 (Channel Control Register) * Bits15-14 for Access Method Figure 80. Transmit Status Block Register (TSBR) Address: none * Must be programmed ...
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Z ILOG ABSOLUTE MAXIMUM RATINGS Symbol Description Min V Supply Voltage (*) –0 Storage Temp –65° STG T Oper Ambient Temp A Power Dissipation Notes: * Voltage on all pins with respect to GND. † See Ordering Information. ...
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Z ILOG IUSC TIMING The IUSC interface timing is similar to that found on a static RAM, except that it is much more flexible four separate timing strobe signals are present on the inter- face: /DS, /RD, /WR ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /AS R//W /DS AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 85. Multiplexed /DS Read Cycle Z16C32 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /AS R//W /DS AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 86. Multiplexed /DS Write Cycle Z16C32 ...
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Z ILOG /CS S//D, D//C /INTACK (Status) /AS /RD AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 87. Multiplexed /RD Read Cycle Z16C32 IUSC ™ 94 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /AS /WR AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 88. Multiplexed /WR Write Cycle Z16C32 IUSC ...
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Z ILOG /CS S//D, D//C /INTACK (Status) R//W /DS AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 89. Non-Multiplexed /DS Read Cycle Z16C32 IUSC ™ 96 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) R//W /DS AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 90. Non-Multiplexed /DS Write Cycle Z16C32 IUSC ...
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Z ILOG /CS S//D, D//C /INTACK (Status) /RD AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 91. Non-Multiplexed /RD Read Cycle Z16C32 IUSC ™ 98 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /WR AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 92. Non-Multiplexed /WR Write Cycle Z16C32 IUSC ™ ...
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Z ILOG /AS /INTACK (Status) /DS AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 93. Multiplexed /DS Interrupt Acknowledge Cycle PS97USC0200 Z16C32 IUSC ™ 100 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /AS /INTACK (Status) /RD AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 94. Multiplexed /RD Interrupt Acknowledge Cycle 101 Z16C32 IUSC ...
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Z ILOG /AS /INTACK (Pulsed) AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 95. Multiplexed Pulsed Interrupt Acknowledge Cycle PS97USC0200 Z16C32 IUSC ™ 102 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /INTACK (Status) /DS AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 96. Non-Multiplexed /DS Interrupt Acknowledge Cycle 103 Z16C32 IUSC ™ ...
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Z ILOG /INTACK (Status) /RD AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 97. Non-Multiplexed /RD Pulsed Interrupt Acknowledge Cycle PS97USC0200 Z16C32 IUSC ™ 104 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /INTACK (Pulsed) AD15-AD0 /WAIT//RDY (Ready) IEI IEO /INT /WAIT//RDY (Wait) Figure 98. Non-Multiplexed Pulsed Interrupt Acknowledge Cycle 105 Z16C32 IUSC ™ PS97USC0200 ...
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Z ILOG /AS /INTACK (2-Pulse) AD15-AD0 /WAIT//RDY (Ready) /WAIT//RDY (Wait) IEI IEO /INT Figure 99. Multiplexed Double-Pulse Intack Cycle PS97USC0200 Z16C32 IUSC ™ 106 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /INTACK (2-Pulse) AD15-AD0 /WAIT//RDY (Ready) /WAIT//RDY (Wait) IEI IEO /INT Figure 100. Non-Multiplexed Double-Pulse Intack Cycle 107 Z16C32 IUSC ™ PS97USC0200 ...
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Z ILOG CLK /UAS /AS /DS R//W /RD /WR S//D, D//C AD15-AD0 /BUSREQ /BIN PS97USC0200 Figure 101. DMA Start-Up Z16C32 IUSC ™ 108 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) CLK /UAS /AS /DS R//W /RD S//D, D//C AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) /BIN /ABORT 109 Figure 102. Memory Read Z16C32 IUSC ...
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Z ILOG CLK /UAS /AS /DS R//W /WR S//D, D//C AD15-AD0 /WAIT//RDY (Ready) /WAIT//RDY (Wait) /BIN /ABORT PS97USC0200 Figure 103. Memory Write Z16C32 IUSC ™ 110 ...
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Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) CLK /UAS /AS /DS R//W /RD /WR S//D, D//C AD15-AD0 111 Figure 104. Bus Release Z16C32 IUSC ™ PS97USC0200 ...
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Z ILOG CLK /BUSREQ /BIN /BOUT PS97USC0200 Figure 105. Request Timing Z16C32 IUSC ™ 112 ...
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Z ILOG AC CHARACTERISTICS Timing Table No Symbol Parameter 1 Tcyc Bus Cycle Time 2 TwASl /AS Low Width 3 TwASh /AS High Width 4 TwDSl /DS Low Width 5 TwDSh /DS High Width 6 TdAS(DS) /AS Rise to /DS ...
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Z ILOG No Symbol Parameter 45 TdWRr(TRQ) /WR Rise to /TxREQ Active Delay 46 TsCS(DS) /CS to /DS Fall Setup Time 47 ThCS(DS) /CS to /DS Fall Hold Time 48 TsADD(DS) Direct Address to /DS Fall Setup Time 49 ThADD(DS) ...
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Z ILOG AC CHARACTERISTICS (Continued) Timing Table No Symbol Parameter 103 TsIEI(PIA) IEI to Pulsed /INTACK Fall Setup Time 104 ThIEI(PIA) IEI to Pulsed /INTACK Rise Hold Time 105 TdPIA(IEO) Pulsed /INTACK Fall to IEO Delay 106 TdPIA(INT) Pulsed /INTACK ...
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Z ILOG No Symbol Parameter 147 TdCLK(ADz) CLK Rise to Address Float Delay 148 TdCLK(ADa) CLK Rise to Address Active Delay 149 TsAD(UAS) Address to /UAS Rise Setup Time 150 ThAD(UAS) Address to /UAS Rise Hold Time 151 TsAD(AS) Address ...
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Z ILOG AC CHARACTERISTICS General Timing Diagram /RxC, /TxC Receive RxD /DCD as /SYNC External /TxC, /RxC Transmit TxD /RxC /TxC /CTS, /DCD /DCD as /SYNC Input 117 Figure ...
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Z ILOG AC CHARACTERISTICS General Timing Table No Symbol Parameter 1 TsRxD(RxCr) RxD to /RxC Rise Setup Time (x1 Mode) 2 ThRxD(RxCr) RxD to /RxC Rise Hold Time (x1 Mode) 3 TsRxd(RxCf) RxD to /RxC Fall Setup Time (x1 Mode) ...
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Z ILOG AC CHARACTERISTICS System Timing Diagram /RxC, /TxC Receive /RxREQ Request /RxC as Receiver Output /INT /RxC, /TxC Transmit /TxREQ /TxC as Transmitter Output /INT /CTS, /DCD, /TxREQ, /RxREQ /INT 119 ...
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Z ILOG AC CHARACTERISTICS System Timing Table No Symbol Parameter 1 TdRxC(REQ) /RxC Rise to /RxREQ Valid Delay 2 TdRxC(RxC) /TxC Rise to /RxC as Receiver Output Valid Delay 3 TdRxC(INT) /RxC Rise to /INT Valid Delay 4 TdTxC(REQ) /TxC ...
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Z ILOG PACKAGE INFORMATION 121 68-Pin PLCC Package Diagram Z16C32 IUSC ™ PS97USC0200 ...
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... Z ILOG ORDERING INFORMATION Z16C32 IUSC 20 MHz 68-Pin PLCC Z16C3220VSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package V = Plastic Chip Carrier Temperature S = 0°C to 70°C Speed MHz Environmental C = Plastic Standard Example: Z 16C32 Z16C32, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow ...