ADV7202KST Analog Devices Inc, ADV7202KST Datasheet - Page 15

• Manufacturer Part Number: ADV7202KST
• Description: IC CODEC VIDEO 10BIT 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV7202KST

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 12, 10 b
• Number Of Adcs / Dacs: 1 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Not Compliant

REV. 0
REGISTER ACCESS
The MPU can write to or read from all of the registers of the
ADV7202 except the Subaddress Registers, which are write-only.
The Subaddress Register determines which register the next read
or write operation accesses. All communications with the part
through the bus start with an access to the Subaddress Register.
A read/write operation is then performed from/to the target
address which then increments to the next address until a Stop
command on the bus is performed.
DOUT [9:0]
XTAL0
SR7
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
Figure 14. Standard Mode Digital Data O/P Format
SR6
DATA
SR6 SR5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA
Figure 15. Subaddress Registers
SR5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SR4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DATA
SR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
SR4
ADV7202 REGISTER
1
SR2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
–15–
DATA
REGISTER PROGRAMMING
The following section describes the functionality of each register.
All registers can be read from as well as written to.
Subaddress Register (SR7–SR0)
The Communications Register is an 8-bit write-only register. After
the part has been accessed over the bus, and a read/write operation
is selected, the subaddress is set up. The Subaddress Register
determines to/from which register the operation takes place.
Figure 15 shows the various operations under the control of the
Subaddress Register. “0” should always be written to SR7.
Register Select (SR6–SR0)
These bits are set up to point to the required starting address.
SR1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
SR3
SR0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
DATA
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
AGC REGISTER 0
AGC REGISTER 1
CLAMP REGISTER 0
CLAMP REGISTER 1
CLAMP REGISTER 2
CLAMP REGISTER 3
TIMING REGISTER
V
RESERVED
RESERVED
RESERVED
RESERVED
AUX REGISTER 0
AUX REGISTER 1
AUX REGISTER 2
AUX REGISTER 3
AUX REGISTER 4
AUX REGISTER 5
AUX REGISTER 6
AUX REGISTER 7
REF
SR2
ADJUST REGISTER
DATA
SR1
DATA
SR0
DATA
ADV7202