CS42526-CQZ Cirrus Logic Inc, CS42526-CQZ Datasheet - Page 49

• Manufacturer Part Number: CS42526-CQZ
• Description: IC CODEC S/PDIF RCVR 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: General Purposer

Specifications of CS42526-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPS
• Interface Type: Serial (SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/6 DAC
• Thd Plus Noise: - 100 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1037

DS585F1
6.4.4
6.4.5
DAC DE-EMPHASIS CONTROL (DAC_DEM)
RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM)
Default = 0
Function:
Default = 0
Function:
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless
of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect
sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the
Receiver Mode Control (address 1Eh) register to set the appropriate sample rate.
When enabled, de-emphasis will be automatically applied when emphasis is detected based on the
channel status bits. The appropriate digital filter will be selected to maintain the standard 15µs/50µs
digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. If
the FRC_PLL_LK bit is set to a ‘1’b, then the auto-detect sample rate feature is disabled. To apply
the correct de-emphasis filter, use the DE-EMPH bits in the Receiver Mode Control (address 1Eh)
register to set the appropriate sample rate.
RCVR_DEM
DAC_DEM
reg03h[1]
reg03h[0]
0
1
1
0
1
1
FRC_PLL_LK
FRC_PLL_LK
reg06h[0]
reg06h[0]
Table 6. Receiver De-Emphasis
X
0
1
X
0
1
Table 5. DAC De-Emphasis
DE-EMPH[1:0]
DE-EMPH[1:0]
reg1Eh[5:4]
reg1Eh[5:4]
XX
XX
XX
XX
00
01
10
11
00
01
10
11
No De-Emphasis
No De-Emphasis
De-Emphasis
De-Emphasis
Auto-Detect Fs
Auto-Detect Fs
Reserved
Reserved
44.1 kHz
44.1 kHz
32 kHz
48 kHz
32 kHz
48 kHz
Mode
Mode
CS42526
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