CS42L52-CNZ Cirrus Logic Inc, CS42L52-CNZ Datasheet - Page 48

• Manufacturer Part Number: CS42L52-CNZ
• Description: IC CODEC STER HDPN & SPKR 40QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L52-CNZ

• Package / Case: 40-QFN
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 99 / 98
• Voltage - Supply, Analog: 1.65 V ~ 2.63 V
• Voltage - Supply, Digital: 1.65 V ~ 2.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Package: 40QFN EP
• Adc/dac Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Number Of Dacs: 2
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1580 - REFERENCE DESIGN FOR CS42L52598-1508 - BOARD EVAL FOR 42LDB1 CODEC598-1505 - BOARD EVAL FOR CS42L52 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1628

48
6.7.3
6.7.4
6.7.5
6.8
6.8.1
ADCASEL2
7
Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)
Tri-State Serial Port Interface
Determines the state of the serial port drivers.
Notes:
1. Slave/Master Mode is determined by the M/S bit in
2. When the serial port is tri-stated in master mode, the ADC and DAC serial ports are clocked internally.
Speaker/Headphone Switch Invert
Determines the control signal polarity of the SPK/HP_SW pin.
MIC Bias Level
Sets the output voltage level on the MICBIAS output pin.
ADC Input Select
Selects the specified analog input signal into ADCx.
INV_SWCH
0
1
BIASLVL[2:0]
000
001
010
011
100
101
110
111
ADCxSEL[2:0]
000
001
010
011
100
101
110
111
Application:
3ST_SP
0
1
ADCASEL1
6
Serial Port Status
Slave Mode
Serial Port clocks are inputs and SDOUT is output
Serial Port clocks are inputs and SDOUT is HI-Z
SPK/HP_SW pin 6 Control
Not inverted
Inverted
Output Bias Level
0.5 x VA
0.6 x VA
0.7 x VA
0.8 x VA
0.83 x VA
0.91 x VA
Reserved
Reserved
Selected Input to ADCx
AIN1x
AIN2x
AIN3x
AIN4x
PGAx - Use PGAxSEL bits
Reserved
Reserved
Reserved
“Analog Inputs” on page 26
ADCASEL0
5
PGAASEL5
(“PGA Input Mapping” on page
4
5/13/08
PGAASEL4
“Master/Slave Mode” on page
3
Master Mode
Serial Port clocks and SDOUT are outputs
Serial Port clocks and SDOUT are HI-Z
49) to select input channels
PGAASEL3
2
PGAASEL2
1
46.
CS42L52
PGAASEL1
DS680F1
0