MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 260
MC68020RC20E
Manufacturer Part Number
MC68020RC20E
Description
IC MICROPROCESSOR 32BIT 114-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68020EH16E.pdf
(306 pages)
Specifications of MC68020RC20E
Processor Type
M680x0 32-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
114-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
114
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68020RC20E
Manufacturer:
FREESCALE
Quantity:
1 831
Part Number:
MC68020RC20E
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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During cachable read cycles, the addressed device must provide valid data over its full
bus width as indicated by DSACK1 / DSACK0 . While instructions are always prefetched as
long-word-aligned accesses, data fetches can occur with any alignment and size.
Because the MC68020/EC020 assumes that the entire data bus port size contains valid
data, cachable data read bus cycles must provide as much data as signaled by the port
size during a bus cycle. To satisfy this requirement, the R/ W signal must be included in
the byte select logic for the MC68020/EC020.
Figure 9-5 shows a block diagram of an MC68020/EC020 system with a single memory
bank. The PAL provides memory-mapped byte select signals for an asynchronous 32-bit
port and unmapped byte select signals for other memory banks or ports. Figure 9-6
provides sample equations for the PAL.
The PAL equations and circuits presented here cannot be the optimal implementation for
every system. Depending on the CPU clock frequency, memory access times, and system
architecture, different circuits may be required.
9-6
Byte
Word
3 Bytes
Long Word
Transfer Size
Table 9-1. Data Bus Activity for Byte, Word, and Long-Word Ports
SIZ1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
SIZ0
Freescale Semiconductor, Inc.
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
For More Information On This Product,
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M68020 USER’S MANUAL
Go to: www.freescale.com
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D31–D24
B W L
B W L
B W L
B W L
B W
B W
B W
B W
B
B
B
B
B
B
B
B
Byte (B), Word (W), Long-Word (L) Ports
Data Bus Active Sections
D23–D16
W L
W L
W L
W L
W L
W L
W L
—
—
W
W
W
W
W
W
W
D15–D8
—
—
—
—
—
—
—
L
L
L
L
L
L
L
L
L
MOTOROLA
D7–D0
—
—
—
—
—
—
L
L
L
L
L
L
L
L
L
L
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