TSPC603RVGH8LC Atmel, TSPC603RVGH8LC Datasheet - Page 35

• Manufacturer Part Number: TSPC603RVGH8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

12.2.2
12.3
12.3.1
12.3.2
5410B–HIREL–09/05
Cache Implementation
PowerPC 603R Microprocessor Instruction Set
PowerPC Cache Characteristics
PowerPC 603R Microprocessor Cache Implementation
The 603R instruction set is defined as follows:
The following subsections describe the way the PowerPC architecture deals with cache in gen-
eral, and the 603R’s specific implementation.
The PowerPC architecture does not define hardware aspects of cache implementations. For
example, some PowerPC processors, including the 603R, have separate instruction and data
caches (harvard architecture).
The PowerPC microprocessor controls the following memory access modes on a page or block
basis:
Note that in the 603R, a cache line is defined as eight words. The VEA defines cache manage-
ment instructions that provide a means by which the application programmer can affect the
cache contents.
The 603R has two 16-Kbyte, four-way set-associative (instruction and data) caches. The caches
are physically addressed, and the data cache can operate in either write-back or write-through
modes as specified by the PowerPC architecture.
The data cache is configured as 128 sets of four lines each. Each line consists of 32 bytes, two
state bits, and an address tag. The two state bits implement the three-state MEI (Modified/Exclu-
sive/Invalid) protocol. Each line contains eight 32-bit words. Note that the PowerPC architecture
defines the term block as the cacheable unit. For the 603R, the block size is equivalent to a
cache line. A block diagram of the data cache organization is shown in
• The 603R provides hardware support for all 32-bit PowerPC instructions.
• The 603R provides two implementation-specific instructions used for software table search
• The 603R implements the following instructions which are defined as optional by the
• Write-back/write-through mode
• Cache-inhibited mode
• Memory coherency
operations following TLB misses:
PowerPC architecture :
– Load Data TLB Entry (tlbld)
– Load Instruction TLB Entry (tlbli)
– External Control in Word Indexed (eciwx)
– External Control Out Word Indexed (ecowx)
– Floating Select (fsed)
– Floating Reciprocal Estimate Single-Precision (fres)
– Floating Reciprocal Square Root Estimate (frsqrte)
– Store Floating-Point as Integer Word (stfiwx)
Figure 12-2 on page
TSPC603R
36.
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