TSPC603RVGH8LC Atmel, TSPC603RVGH8LC Datasheet - Page 24

• Manufacturer Part Number: TSPC603RVGH8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

11.3.2
Table 11-3.
Notes:
24
Number
Figure
10a
10b
10c
11a
11b
11c
1. All input specifications are measured from the TTL level (0.8 or 2V) of the signal in question to the 1.4V of the rising edge of
2. Address/data/transfer attribute input signals are composed of the following: A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST,
3. All other input signals are composed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA,
4. The setup and hold time is with respect to the rising edge of HRESET. See
5. t
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus
TSPC603R
Input AC Specifications
the input SYSCLK. Both input and output timings are measured at the pin. See
TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[9-7].
DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
clocks after the PLL relock time (100 µs) during the power-on reset sequence.
sysclk
Characteristics
Address/data/transfer attribute inputs valid to
SYSCLK (input setup)
All other inputs valid to SYSCLK (input setup)
Mode select inputs valid to HRESET (input
setup) (for DRTRY, QACK and TLBISYNC)
SYSCLK to address/data/transfer attribute
inputs invalid (input hold)
SYSCLK to all other inputs invalid (input hold)
HRESET to mode select inputs invalid (input
hold) (for DRTRY, QACK, and TLBISYNC)
Input AC Timing Specifications
-55°C ≤ T
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
C
≤ 125°C
Table 11-3
and
Figure 11-2. Input Timing Diagram
All inputs
SYSCLK
Figure
10a
10b
11-3.
provides the input AC timing specifications for the 603R as defined in
(1)
with
VM
V
DD
= A
CBGA 255, CI-CGA
CBGA 255, HiTCE
255 and Cerquad
11a
11b
Min
2.5
240 Packages
166, 200 MHz
4
8
1
1
0
V
DD
= 2.5V ±5%; O
VM = Midpoint Voltage (1.4V)
Max
–
–
–
–
–
–
CBGA 255, HiTCE CBGA 255
233, 266 MHz
V
Figure
Min
2.5
3.5
DD
8
1
1
0
Figure
= 3.3 ±5%V, GND = 0V,
and CI-CGA 255
11-3.
Max
–
–
–
–
–
–
11-3.
Min
2.5
3.5
8
1
1
0
300 MHz
Max
–
–
–
–
–
–
5410B–HIREL–09/05
Unit
t
syscl
ns
ns
ns
ns
ns
Figure 11-2
k
(4)(5)(6
Note
(4)(6)
)(7)
(2)
(3)
(2)
(3)
(7)