IDT79R3041-25PF IDT, Integrated Device Technology Inc, IDT79R3041-25PF Datasheet - Page 13

• Manufacturer Part Number: IDT79R3041-25PF
• Description: IC MPU 32BIT 5V 25MHZ 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R3041-25PF

• Processor Type: RISC 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R3041-25PF

PIN DESCRIPTION (Continued):
NOTE:
1. Reset Configuration Mode bit input when
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
PIN NAME
BE16(1:0)
Last
TC
BusError
Int(5:3)
SInt(2:0)
ClkIn
Reset
TriState
Vcc
Vss
function when
Reset
O
I
O
O
I
I
I
I
I
I
I
I
(1)
(1)
I/O
is de-asserted.
Byte Enable Strobes for 16-bit Memory Port: These active low outputs are the byte lane strobes for
accesses to 16-bit wide memory ports; they are not necessarily valid for 8- or 32-bit wide ports. If
is asserted, then the most significant byte (either D(31:24) or D(15:8), depending on system endianness)
is going to be used in this transfer. If
will be used.
BE16(1:0)
Bus Control register.
During
The
Last Datum in Mini-Burst: This active low output indicates that this is the last datum transfer in a given
transaction. It is asserted after the next to last
or
The
Terminal Count: This is an active low output from the processor which indicates that the on-chip timer
has reached its terminal count. It will remain low for either 1.5 clock cycles, or until software resets the
timer, depending on the mode selected in the CP0 Bus Control register. Thus, the on-chip timer can
function either as a free running timer for system functions such as DRAM refresh, or can operate as a
software controlled time-slice timer, or real-time clock.
The
pin output.
Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.
Processor Interrupt: During normal operation, these signals are logically the same as the
signals of the R3000A. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals on the original R3000A.
During
AddrDisplayAndForceCacheMiss
There are two types of interrupt inputs: the
and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.
Master Clock Input: This is a double frequency input used to control the timing of the CPU.
Master Processor Reset: This signal initializes the CPU. Reset initialization mode selection is
performed during the last cycle of
Tri-State: This input to the R3041 requests that the R3041 tri-state all of its outputs. In addition to those
outputs tri-stated during DMA, tri-state will cause
intended for use during board testing and emulation during debug and board manufacture.
The
Power: These inputs must be supplied with the rated supply voltage (VCC). All Vcc inputs must be
connected to insure proper operation.
Ground: These inputs must be connected to ground (GND). All Vss inputs must be connected to insure
proper operation.
Wr
BE16(1:0)
Last
TC
TriState
Reset
is negated.
Reset
Reset
output pin is designated in the R3051 as the BrCond(1) input pin, and in the R3081 as the Run
output pin is designated in the R3051 and R3081 as the Diag(0) output pin.
can be held inactive (masked) during read transfers, according to the programming of the CP0
is asserted, normal signal
input pin is designated as the unconnected Rsvd(4)pin in the R3051 and R3081.
, the
,
Int(3)
output pins are designated as the unconnected Rsvd(3:2) pins in the R3051 and R3081.
BE16(1:0)
and
SInt(0)
act as Reset Configuration Mode bit inputs for two ReservedHigh options.
act as Reset Configuration Mode bit inputs for the
Reset
and BigEndian options.
BE16(0)
DESCRIPTION
.
SInt
is asserted, the least significant byte (D(23:16) or D(7:0))
RdCEn
inputs are internally synchronized by the processor,
SysClk
(reads) or
,
TC
, and
Ack
COMMERCIAL TEMPERATURE RANGE
BusGnt
(writes), and is negated when
to tri-state. This signal is
Int
BE16(1
(5:0)
2905 tbl 05
13
Rd
)