IDT79R3041-25PF IDT, Integrated Device Technology Inc, IDT79R3041-25PF Datasheet - Page 11

• Manufacturer Part Number: IDT79R3041-25PF
• Description: IC MPU 32BIT 5V 25MHZ 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R3041-25PF

• Processor Type: RISC 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R3041-25PF

PIN DESCRIPTION
NOTE:
1. Reset Configuration Mode bit input when
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
PIN NAME
A/D(31:0)
Addr(3:0)
Diag
ALE
DataEn
system onto this bus without having a bus conflict occur. During write cycles, or when no bus
action is occurring, this signal is negated, thus disabling the external memory drivers.
function when
Reset
I/O
I/O
O
I
O
O
O
during read cycles, and thus the external memory system may enable the drivers of the memory
(1)
is de-asserted.
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
During the second phase, these signals are the data bus for the transaction.
Low Address (3:0) A 4-bit bus which indicates which word/halfword/byte is currently expected by the
processor. For 32-bit port widths, only Addr(3:2) is valid during the transfer; for 16-bit port widths, only
Addr(3:1) are valid; for 8-bit port widths, all of Addr(3:0) are valid. These address lines always contain
the address of the current datum to be transferred. In writes and single datum reads, the addresses initially
output the specific target address, and will increment if the size of the datum is wider than the target
memory port. For quad word reads, these outputs function as a counter starting at '0000', and
incrementing according to the width of the memory port.
During
BootProm8
The R3041 Addr(1:0) output pins are designated as the unconnected Rsvd(1:0) pins in the R3051 and
R3081.
Diagnostic Pin. This output indicates whether the current bus read transaction is due to an on-
chip cache miss and whether the read is an instruction or data. It is time multiplexed as described below:
The R3041 Diag output pin is designated as the Diag(1) output pin in the R3051 and R3081.
Address Latch Enable: Used to indicate that the A/D bus contains valid address information for
the bus transaction. This signal is used by external logic to capture the address for the transfer, typically
by using transparent latches.
Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor
Address(31:4):
BE(3:0):
Data(31:0):
Cached/
I/
D:
Reset
Reset
, ReservedHigh, and
is asserted, normal signal
, the Addr(3:0) pins act as Reset Configuration Mode bit inputs for the
Uncached
:
The high-order address for the transfer is presented on A/D(31:4).
These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on A/D(3:0).
A/D(31:24) will be used, and
strobes are only valid for accesses to 32-bit wide memory ports. Note
that
bit of CP0; thus when latched, these signals can be directly used as Write
Enable strobes.
During write cycles, the bus contains the data to be stored and is driven
from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in
either a single data transaction or in a burst of four words, and places it
into the on-chip read buffer.
The byte lanes used during the transfer are a function of the datum size,
the memory port width, and the system byte-ordering.
During the phase in which the A/D bus presents address information, this
pin is an active high output which indicates whether or not the current
read is a result of a cache miss. The value of this pin at this time other
than in read cycles is undefined.
A high at this time indicates an instruction reference, and a low indicates
a data reference. The value of this pin at this time other than in read
cycles is undefined.
ExtAddrHold
DESCRIPTION
BE(3:0)
can be held in-active during reads by setting the appropriate
options.
BE(0)
COMMERCIAL TEMPERATURE RANGE
corresponds to A/D(7:0). These
BE(3
) indicates that
BootProm16
trans-
,
2905 tbl 03
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