MPC8315ECVRAGDA Freescale Semiconductor, MPC8315ECVRAGDA Datasheet - Page 30

• Manufacturer Part Number: MPC8315ECVRAGDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8315ECVRAGDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Ethernet: Three-Speed Ethernet, MII Management
Figure 15
9.2.3
Table 29
30
At recommended operating conditions (see
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock cycle duration
Duty cycle for 1000Base-T
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
Fall time (20%–80%)
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
3. For 10 and 100 Mbps, t
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
5. Duty cycle reference is LVDD/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
RGMII and RTBI timing. For example, the subscript of t
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
to the associated clock signal.
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between.
GTX_CLK supply voltage is fixed at 3.3V inside the chip. If PHY supplies a 2.5 V Clock signal on this input, set TSCOMOBI
bit of System I/O configuration register (SICRH) as 1. See the MPC8315E PowerQUICC™ II Pro Integrated Host Processor
Family Reference Manual .
presents the RGMII and RTBI AC timing specifications.
shows the RMII receive AC timing diagram.
RGMII and RTBI AC Timing
Parameter/Condition
REF_CLK
RXD[1:0]
CRS_DV
RX_ER
3
MPC8315E PowerQUICC
RGT
4, 5
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
Table 29. RGMII and RTBI AC Timing Specifications
Figure 15. RMII Receive AC Timing Diagram
2
t
RMRDVKH
Table
t
RMXH
2)
3, 5
t
RMX
™
II Pro Processor Hardware Specifications, Rev. 0
Valid Data
RGT
t
Specifications
t
t
G125H
Symbol
RGTH
RGTH
represents the RTBI (T) receive (RX) clock. Note also that the
t
t
t
t
SKRGT
SKRGT
t
RGTR
t
RGTF
G12
RGT
t
RMXF
/t
/t
/t
RGT
RGT
G125
6
1
t
RMRDXKH
t
–0.6
RMXR
Min
1.0
7.2
45
40
47
—
—
—
RGT
Typ
8.0
8.0
of the lowest speed transitioned
50
50
—
—
—
—
—
Freescale Semiconductor
Max
0.75
0.75
0.6
2.6
8.8
55
60
53
—
Unit
ns
ns
ns
ns
ns
ns
%
%
%