XC2018-70PC68C Xilinx Inc, XC2018-70PC68C Datasheet - Page 18

• Manufacturer Part Number: XC2018-70PC68C
• Description: IC LOGIC CL ARRAY 1800GAT 68PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC68C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 58
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1003

XC2000 Logic Cell Array Families
Master Parallel Mode
Figure 14. Master Parallel Mode Configuration with Daisy Chained Slave Mode Devices. All are configured from the common
EPROM source. A well defined termination of SYSTEM RESET is needed when controlling multiple LCA devices.
In Master Parallel mode, the lead LCA device directly
addresses an industry-standard byte-wide EPROM and
accepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data (and all data that
overflows the lead device) on the DOUT pin. There is an
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data, and also changes the
REPROGRAM
SYSTEM RESET
General-
Purpose
User I/O
+5 V
Pins
5 k
M2
HDC
RCLK
D7
D6
D5
D4
D3
D2
D1
D0
D/P
RESET
Other
I/O Pins
M0 M1 PWRDWN
*
Master
LCA
+5 V
DOUT
CCLK
LDC
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CE
8
EPROM
D7
D6
D5
D4
D3
D2
D1
D0
Collector
Open
2-202
+5 V
EPROM address, until the falling CCLK edge that makes
the LSB (D0) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy-chain accepts data on the subse-
quent rising CCLK edge.
Any XC3000 slave driven by an XC2000 master mode
device must use early DONE and early internal reset.
(The XC2000 master will not supply the extra clock re-
quired by a late programmed XC3000.)
D/P
CCLK
DIN
RESET
M0 M1 PWRDWN
*
Slave #1
LCA
I/O Pins
Other
DOUT
HDC
LDC
M2
5 k
General-
Purpose
User I/O
Pins
• • •
+5 V
D/P
CCLK
DIN
RESET
5 k
M0 M1 PWRDWN
NOTE: Reset of a master
device should be asserted
by an external timing
circuit to allow for LCA CCLK
variations in clear state time.
*
If readback is
activated, a
5 k resistor is
required in
series with M1
*
Slave #n
LCA
+5 V
I/O Pins
Other
DOUT
HDC
LDC
M2
5 k
General-
Purpose
User I/O
Pins
X5407