XCV812E-7FG900C Xilinx Inc, XCV812E-7FG900C Datasheet - Page 10

• Manufacturer Part Number: XCV812E-7FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-7FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 5
block SelectRAM. The Virtex-E block SelectRAM also
includes dedicated routing to provide an efficient interface
with both CLBs and other block SelectRAM modules. Refer
to XAPP130 for block SelectRAM timing waveforms.
Table 5:
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex-E routing
architecture and its place-and-route software were defined
in a joint optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
Local Routing
The VersaBlock, shown in
resources with the following types of connections:
•
•
•
Module 2 of 4
6
Width
Interconnections among the LUTs, flip-flops, and GRM
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
16
1
2
4
8
shows the depth and width aspect ratios for the
Figure 6: Dual-Port Block SelectRAM
Block SelectRAM Port Aspect Ratios
Depth
4096
2048
1024
512
256
WEA
ENA
RSTA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
ADDRB[#:0]
DIB[#:0]
CLKA
CLKB
RAMB4_S#_S#
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
ADDR Bus
Figure
DOA[#:0]
DOB[#:0]
7, provides local routing
ds022_06_121699
DATA<15:0>
DATA<1:0>
DATA<3:0>
DATA<7:0>
Data Bus
DATA<0>
www.xilinx.com
1-800-255-7778
.
General Purpose Routing
Most Virtex-E signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. The general routing resources are located in horizon-
tal and vertical routing channels associated with the CLB
rows and columns. The general-purpose routing resources
are listed below.
•
•
•
•
I/O Routing
Virtex-E devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the VersaRing,
facilitates pin-swapping and pin-locking, such that logic
redesigns can adapt to existing PCB layouts. Time-to-mar-
ket is reduced, since PCBs and other system components
can be manufactured while the logic design is still in
progress.
delay of the GRM
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
are driven only at their endpoints. Hex-line signals can
be accessed either at the endpoints or at the midpoint
(three blocks from the source). One third of the Hex
lines are bidirectional, while the remaining ones are
uni-directional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
Adjacent
GRM
To
Figure 7: Virtex-E Local Routing
Direct Connection
To Adjacent
To Adjacent
To Adjacent
GRM
GRM
GRM
CLB
DS025-2 (v2.3) November 19, 2002
To Adjacent
GRM
CLB
Direct
Connection
To Adjacent
CLB
XCVE_ds_007
R