EP1SGX25FF1020C5 Altera, EP1SGX25FF1020C5 Datasheet - Page 177

no-image

EP1SGX25FF1020C5

Manufacturer Part Number
EP1SGX25FF1020C5
Description
IC STRATIX GX FPGA 25K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX25FF1020C5

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
607
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
25660
# I/os (max)
607
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX25FF1020C5
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX25FF1020C5
Manufacturer:
ALTERA
0
Part Number:
EP1SGX25FF1020C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1SGX25FF1020C5ES
Manufacturer:
ALTERA
0
Part Number:
EP1SGX25FF1020C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1SGX25FF1020C5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX25FF1020C5N
Manufacturer:
ALTERA
0
Altera Corporation
February 2005
Table 4–24
strength control.
The Quartus II software, beginning with version 4.2, reports current
strength as “PCI Compliant” for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact
PCI I/O standards.
Stratix GX devices support series on-chip termination (OCT) using
programmable drive strength. For more information, contact your Altera
Support Representative.
Open-Drain Output
Stratix GX devices provide an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (that is, interrupt and
write-enable signals) that can be asserted by any of several devices.
Notes to
(1)
(2)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
GTL/GTL+
1.5-V HSTL class I and II
1.8-V HSTL class I and II
SSTL-3 class I and II
SSTL-2 class I and II
SSTL-18 class I and II
Table 4–24. Programmable Drive Strength
This is the Quartus II software default current setting.
I/O banks 1 and 2 do not support this setting.
Table
I/O Standard
shows the possible settings for the I/O standards with drive
4–24:
24 (1), 16, 12, 8, 4
24 (2), 12 (1), 8, 4, 2
16 (1), 12, 8, 2
12 (1), 8, 2
8 (1), 4, 2
Support maximum and minimum strength
Stratix GX Device Handbook, Volume 1
I
OH
/ I
OL
Current Strength Setting (mA)
Stratix GX Architecture
4–111

Related parts for EP1SGX25FF1020C5