ADSP-2101BS-100 Analog Devices Inc, ADSP-2101BS-100 Datasheet - Page 44

• Manufacturer Part Number: ADSP-2101BS-100
• Description: IC DSP CONTROLLER 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2101BS-100

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 25MHz
• Non-volatile Memory: External
• On-chip Ram: 6kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 25MHz
• Mips: 25
• Device Input Clock Speed: 25MHz
• Ram Size: 3KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Memory Specification
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
ADSP-21xx
Timing Parameter
t
t
t
t
t
t
t
ASW
AW
WRA
DW
DH
RDD
AA
–44–
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
Timing Parameter Definition
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
REV. B