ADSP-21991BST Analog Devices Inc, ADSP-21991BST Datasheet - Page 9

• Manufacturer Part Number: ADSP-21991BST
• Description: IC DSP CONTROLLER 16BIT 176LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-21991BST

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP

The ADSP-21991 integrates a flexible and programmable, 3-
phase PWM waveform generator that can be programmed to
generate the required switching patterns to drive a 3-phase
voltage source inverter for ac induction (ACIM) or permanent
magnet synchronous (PMSM) motor control. In addition, the
PWM block contains special functions that considerably simplify
the generation of the required PWM switching patterns for
control of the electronically commutated motor (ECM) or
brushless dc motor (BDCM). Tying a dedicated pin, PWMSR,
to GND, enables a special mode, for switched reluctance motors
(SRM).
The six PWM output signals consist of three high side drive pins
(AH, BH, and CH) and three low side drive signals pins (AL,
BL, and CL). The polarity of the generated PWM signals may
be set via hardware by the PWMPOL input pin, so that either
active HI or active LO PWM patterns can be produced.
The switching frequency of the generated PWM patterns is pro-
grammable using the 16-bit PWMTM register. The PWM
generator is capable of operating in two distinct modes, single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period,
so that the resultant PWM patterns are symmetrical about the
midpoint of the PWM period. In the double update mode, a
second updating of the PWM registers is implemented at the
midpoint of the PWM period. In this mode, it is possible to
produce asymmetrical PWM patterns that produce lower
harmonic distortion in 3-phase PWM inverters.
Auxiliary PWM Generation Unit
Key features of the auxiliary PWM generation unit are:
• 16-bit, programmable frequency, programmable duty
• Independent or offset operating modes
• Double buffered control of duty cycle and period registers
• Separate auxiliary PWM synchronization signal and asso-
• Separate auxiliary PWM shutdown signal (AUXTRIP).
The ADSP-21991 integrates a 2-channel, 16-bit, auxiliary PWM
output unit that can be programmed with variable frequency,
variable duty cycle values and may operate in two different
modes, independent mode or offset mode. In independent mode,
the two auxiliary PWM generators are completely independent
and separate switching frequencies and duty cycles may be pro-
grammed for each auxiliary PWM output. In offset mode the
switching frequency of the two signals on the AUX0 and AUX1
pins is identical. Bit 4 of the AUXCTRL register places the
auxiliary PWM channel pair in independent or offset mode.
The Auxiliary PWM generation unit provides two chip output
pins, AUX0 and AUX1 (on which the switching signals appear),
and one chip input pin, AUXTRIP, which can be used to shut
down the switching signals—for example in a fault condition.
REV. 0
cycle PWM outputs
ciated interrupt (can be used to trigger ADC Convert
Start).
–9–
Encoder Interface Unit
The ADSP-21991 incorporates a powerful encoder interface
block to incremental shaft encoders that are often used for
position feedback in high performance motion control systems.
• Quadrature rates to 53 MHz (at 80 MHz HCLK rate).
• Programmable filtering of all encoder input signals
• 32-bit encoder counter
• Variety of hardware and software reset modes
• Two registration inputs to latch EIU count value with
• Status of A/B signals latched with reading of EIU count
• Alternative frequency and direction mode
• Single north marker mode
• Count error monitor function with dedicated error
• Dedicated 16-bit loop timer with dedicated interrupt
• Companion encoder event (1⁄T) timer unit.
The encoder interface unit (EIU) includes a 32-bit quadrature
up/down counter, programmable input noise filtering of the
encoder input signals and the zero markers, and has four
dedicated chip pins. The quadrature encoder signals are applied
at the EIA and EIB pins. Alternatively, a frequency and direction
set of inputs may be applied to the EIA and EIB pins. In addition,
two north marker/strobe inputs are provided on pins EIZ and
EIS. These inputs may be used to latch the contents of the
encoder quadrature counter into dedicated registers,
EIZLATCH and EISLATCH, on the occurrence of external
events at the EIZ and EIS pins. These events may be programmed
to be either rising edge only (latch event) or rising edge if the
encoder is moving in the forward direction and falling edge if the
encoder is moving in the reverse direction (software latched north
marker functionality).
The encoder interface unit incorporates programmable noise
filtering on the four encoder inputs to prevent spurious noise
pulses from adversely affecting the operation of the quadrature
counter. The encoder interface unit operates at a clock frequency
equal to the HCLK rate. The encoder interface unit operates
correctly with encoder signals at frequencies of up to 13.25 MHz
at the 80 MHz HCLK rate, corresponding to a maximum
quadrature frequency of 53 MHz (assuming an ideal quadrature
relationship between the input EIA and EIB signals).
The EIU may be programmed to use the north marker on EIZ
to reset the quadrature encoder in hardware, if required.
Alternatively, the north marker can be ignored, and the encoder
quadrature counter is reset according to the contents of a
maximum count register, EIUMAXCNT. There is also a “single
north marker” mode available in which the encoder quadrature
counter is reset only on the first north marker pulse.
corresponding registration interrupt
value.
interrupt
ADSP-21991